354 lines
16 KiB
Scala
354 lines
16 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util._
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// We detect concurrent puts that put memory into an undefined state.
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// put0, put0Ack, put1, put1Ack => ok: defined
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// put0, put1, put0Ack, put1Ack => ok: put1 clears valid (it sees busy>0) defined for FIFO
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// put0, put1, put1Ack, put0Ack => ok: put1 clears valid (it sees busy>0) defined for FIFO
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// When the region is FIFO, all writes leave 'valid' set (concurrent puts have defined behaviour)
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// We detect concurrent puts that invalidate an inflight get.
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// get, getAck, put, putAck => ok: defined
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// get, put, getAck, putAck => ok: detected by getAck (it sees busy>0)
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// get, put, putAck, getAck => ok: putAck uses CAM to wipe get validity impossible for FIFO
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// put, putAck, get, getAck => ok: defined
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// put, get, putAck, getAck => ok: putAck uses CAM to wipe get validity defined for FIFO
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// put, get, getAck, putAck => ok: detected by getAck (it sees busy>0) impossible for FIFO
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// If FIFO, the getAck should check data even if its validity was wiped
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class TLRAMModel(log: String = "", ignoreErrorData: Boolean = false)(implicit p: Parameters) extends LazyModule
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{
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val node = TLAdapterNode()
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val edge = edgeIn
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val endAddress = edge.manager.maxAddress + 1
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val endSourceId = edge.client.endSourceId
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val maxTransfer = edge.manager.maxTransfer
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val beatBytes = edge.manager.beatBytes
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val endAddressHi = (endAddress / beatBytes).intValue
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val maxLgBeats = log2Up(maxTransfer/beatBytes)
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val shift = log2Ceil(beatBytes)
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val decTrees = log2Up(maxTransfer/beatBytes)
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val addressBits = log2Up(endAddress)
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val countBits = log2Up(endSourceId)
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val sizeBits = edge.bundle.sizeBits
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val divisor = CRC.CRC_16F_4_2
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// Reset control logic
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val wipeIndex = RegInit(UInt(0, width = log2Ceil(endAddressHi) + 1))
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val wipe = !wipeIndex(log2Ceil(endAddressHi))
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wipeIndex := wipeIndex + wipe.asUInt
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// Block traffic while wiping Mems
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in.a.ready := out.a.ready && !wipe
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out.a.valid := in.a.valid && !wipe
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out.a.bits := in.a.bits
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out.d.ready := in.d.ready && !wipe
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in.d.valid := out.d.valid && !wipe
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in.d.bits := out.d.bits
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// BCE unsupported
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in.b.valid := Bool(false)
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out.c.valid := Bool(false)
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out.e.valid := Bool(false)
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out.b.ready := Bool(true)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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val params = TLRAMModel.MonitorParameters(addressBits, sizeBits)
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// Infer as simple dual port BRAM/M10k with write-first/new-data semantics (bypass needed)
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val shadow = Seq.fill(beatBytes) { Mem(endAddressHi, new TLRAMModel.ByteMonitor(params)) }
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val inc_bytes = Seq.fill(beatBytes) { Mem(endAddressHi, UInt(width = countBits)) }
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val dec_bytes = Seq.fill(beatBytes) { Mem(endAddressHi, UInt(width = countBits)) }
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val inc_trees = Seq.tabulate(decTrees) { i => Mem(endAddressHi >> (i+1), UInt(width = countBits)) }
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val dec_trees = Seq.tabulate(decTrees) { i => Mem(endAddressHi >> (i+1), UInt(width = countBits)) }
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val shadow_wen = Wire(init = Fill(beatBytes, wipe))
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val inc_bytes_wen = Wire(init = Fill(beatBytes, wipe))
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val dec_bytes_wen = Wire(init = Fill(beatBytes, wipe))
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val inc_trees_wen = Wire(init = Fill(decTrees, wipe))
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val dec_trees_wen = Wire(init = Fill(decTrees, wipe))
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// This must be registers b/c we build a CAM from it
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val flight = Reg(Vec(endSourceId, new TLRAMModel.FlightMonitor(params)))
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val valid = Reg(Vec(endSourceId, Bool()))
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// We want to cross flight data from A to D in the same cycle (for combinational TL2 devices)
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val a_flight = Wire(new TLRAMModel.FlightMonitor(params))
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a_flight.base := edge.address(in.a.bits)
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a_flight.size := edge.size(in.a.bits)
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a_flight.opcode := in.a.bits.opcode
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when (in.a.fire()) { flight(in.a.bits.source) := a_flight }
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val bypass = if (edge.manager.minLatency > 0) Bool(false) else in.a.valid && in.a.bits.source === out.d.bits.source
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val d_flight = RegEnable(Mux(bypass, a_flight, flight(out.d.bits.source)), edge.first(out.d))
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// Process A access requests
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val a = Reg(next = in.a.bits)
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val a_fire = Reg(next = in.a.fire(), init = Bool(false))
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val (a_first, a_last, _, a_address_inc) = edge.addr_inc(a, a_fire)
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val a_size = edge.size(a)
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val a_sizeOH = UIntToOH(a_size)
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val a_address = a.address | a_address_inc
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val a_addr_hi = edge.addr_hi(a_address)
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val a_base = edge.address(a)
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val a_mask = edge.mask(a_base, a_size)
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val a_fifo = edge.manager.hasFifoIdFast(a_base) && edge.client.requestFifo(a.source)
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// Grab the concurrency state we need
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val a_inc_bytes = inc_bytes.map(_.read(a_addr_hi))
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val a_dec_bytes = dec_bytes.map(_.read(a_addr_hi))
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val a_inc_trees = inc_trees.zipWithIndex.map{ case (m, i) => m.read(a_addr_hi >> (i+1)) }
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val a_dec_trees = dec_trees.zipWithIndex.map{ case (m, i) => m.read(a_addr_hi >> (i+1)) }
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val a_inc_tree = a_inc_trees.fold(UInt(0))(_ + _)
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val a_dec_tree = a_dec_trees.fold(UInt(0))(_ + _)
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val a_inc = a_inc_bytes.map(_ + a_inc_tree)
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val a_dec = a_dec_bytes.map(_ + a_dec_tree)
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when (a_fire) {
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// Record the request so we can handle it's response
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assert (a.opcode =/= TLMessages.AcquireBlock && a.opcode =/= TLMessages.AcquirePerm)
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// Mark the operation as valid
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valid(a.source) := Bool(true)
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// Increase the per-byte flight counter for the whole transaction
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when (a_first && a.opcode =/= TLMessages.Hint && a.opcode =/= TLMessages.Get) {
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when (a_size <= UInt(shift)) {
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inc_bytes_wen := a_mask
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}
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inc_trees_wen := a_sizeOH >> (shift+1)
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}
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when (a.opcode === TLMessages.PutFullData || a.opcode === TLMessages.PutPartialData ||
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a.opcode === TLMessages.ArithmeticData || a.opcode === TLMessages.LogicalData) {
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shadow_wen := a.mask
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for (i <- 0 until beatBytes) {
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val busy = a_inc(i) - a_dec(i) - (!a_first).asUInt
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val byte = a.data(8*(i+1)-1, 8*i)
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when (a.mask(i)) {
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printf(log + " ")
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when (a.opcode === TLMessages.PutFullData) { printf("PF") }
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when (a.opcode === TLMessages.PutPartialData) { printf("PP") }
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when (a.opcode === TLMessages.ArithmeticData) { printf("A ") }
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when (a.opcode === TLMessages.LogicalData) { printf("L ") }
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printf(" 0x%x := 0x%x #%d %x\n", a_addr_hi << shift | UInt(i), byte, busy, a.param)
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}
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}
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}
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when (a.opcode === TLMessages.Get) {
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printf(log + " G 0x%x - 0x%x\n", a_base, a_base | UIntToOH1(a_size, addressBits))
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}
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}
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val a_waddr = Mux(wipe, wipeIndex, a_addr_hi)
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val a_shadow = shadow.map(_.read(a_waddr))
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val a_known_old = !(Cat(a_shadow.map(!_.valid).reverse) & a_mask).orR
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val alu = Module(new Atomics(a.params))
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alu.io.write := Bool(false)
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alu.io.a := a
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alu.io.data_in := Cat(a_shadow.map(_.value).reverse)
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val crc = Mem(endSourceId, UInt(width = 16))
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val crc_valid = Mem(endSourceId, Bool())
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val a_crc_acc = Mux(a_first, UInt(0), crc(a.source))
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val a_crc_new = Cat(a_shadow.zipWithIndex.map { case (z, i) => Mux(a_mask(i), z.value, UInt(0)) }.reverse)
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val a_crc = CRC(divisor, Cat(a_crc_acc, a_crc_new), 16 + beatBytes*8)
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val a_crc_valid = a_known_old && Mux(a_first, Bool(true), crc_valid(a.source))
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when (a_fire) {
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crc.write(a.source, a_crc)
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crc_valid.write(a.source, a_crc_valid)
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}
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for (i <- 0 until beatBytes) {
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val data = Wire(new TLRAMModel.ByteMonitor(params))
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val busy = a_inc(i) =/= a_dec(i) + (!a_first).asUInt
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val amo = a.opcode === TLMessages.ArithmeticData || a.opcode === TLMessages.LogicalData
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val beat_amo = a.size <= UInt(log2Ceil(beatBytes))
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data.valid := Mux(wipe, Bool(false), (!busy || a_fifo) && (!amo || (a_known_old && beat_amo)))
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data.value := alu.io.data_out(8*(i+1)-1, 8*i)
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when (shadow_wen(i)) {
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shadow(i).write(a_waddr, data)
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}
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}
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for (i <- 0 until beatBytes) {
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val data = Mux(wipe, UInt(0), a_inc_bytes(i) + UInt(1))
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when (inc_bytes_wen(i)) {
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inc_bytes(i).write(a_waddr, data)
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}
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}
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for (i <- 0 until inc_trees.size) {
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val data = Mux(wipe, UInt(0), a_inc_trees(i) + UInt(1))
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when (inc_trees_wen(i)) {
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inc_trees(i).write(a_waddr >> (i+1), data)
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}
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}
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// Process D access responses
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val d = RegNext(out.d.bits)
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val d_fire = Reg(next = out.d.fire(), init = Bool(false))
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val (d_first, d_last, _, d_address_inc) = edge.addr_inc(d, d_fire)
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val d_size = edge.size(d)
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val d_sizeOH = UIntToOH(d_size)
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val d_base = d_flight.base
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val d_address = d_base | d_address_inc
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val d_addr_hi = edge.addr_hi(d_address)
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val d_mask = edge.mask(d_base, d_size)
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val d_fifo = edge.manager.hasFifoIdFast(d_flight.base) && edge.client.requestFifo(d.source)
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// Grab the concurrency state we need
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val d_inc_bytes = inc_bytes.map(_.read(d_addr_hi))
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val d_dec_bytes = dec_bytes.map(_.read(d_addr_hi))
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val d_inc_trees = inc_trees.zipWithIndex.map{ case (m, i) => m.read(d_addr_hi >> (i+1)) }
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val d_dec_trees = dec_trees.zipWithIndex.map{ case (m, i) => m.read(d_addr_hi >> (i+1)) }
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val d_inc_tree = d_inc_trees.fold(UInt(0))(_ + _)
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val d_dec_tree = d_dec_trees.fold(UInt(0))(_ + _)
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val d_inc = d_inc_bytes.map(_ + d_inc_tree)
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val d_dec = d_dec_bytes.map(_ + d_dec_tree)
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val d_shadow = shadow.map(_.read(d_addr_hi))
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val d_valid = valid(d.source) holdUnless d_first
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// CRC check
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val d_crc_reg = Reg(UInt(width = 16))
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val d_crc_acc = Mux(d_first, UInt(0), d_crc_reg)
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val d_crc_new = FillInterleaved(8, d_mask) & d.data
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val d_crc = CRC(divisor, Cat(d_crc_acc, d_crc_new), 16 + beatBytes*8)
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val crc_bypass = if (edge.manager.minLatency > 0) Bool(false) else a_fire && a.source === d.source
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val d_crc_valid = Mux(crc_bypass, a_crc_valid, crc_valid.read(d.source)) holdUnless d_first
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val d_crc_check = Mux(crc_bypass, a_crc, crc.read(d.source)) holdUnless d_first
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val d_no_race_reg = Reg(Bool())
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val d_no_race = Wire(init = d_no_race_reg)
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when (d_fire) {
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d_crc_reg := d_crc
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d_no_race_reg := d_no_race
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// Check the response is correct
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assert (d_size === d_flight.size)
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// addr_lo is allowed to differ
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when (d_flight.opcode === TLMessages.Hint) {
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assert (d.opcode === TLMessages.HintAck)
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}
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// Decrease the per-byte flight counter for the whole transaction
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when (d_last && d_flight.opcode =/= TLMessages.Hint && d_flight.opcode =/= TLMessages.Get) {
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when (d_size <= UInt(shift)) {
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dec_bytes_wen := d_mask
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}
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dec_trees_wen := d_sizeOH >> (shift+1)
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// NOTE: D channel carries uninterrupted multibeast op, so updating on last is fine
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for (i <- 0 until endSourceId) {
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// Does this modification overlap a Get? => wipe it's valid
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val f_base = flight(i).base
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val f_size = flight(i).size
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val f_bits = UIntToOH1(f_size, addressBits)
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val d_bits = UIntToOH1(d_size, addressBits)
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val overlap = ~(~(f_base ^ d_base) | (f_bits | d_bits)) === UInt(0)
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when (overlap) { valid(i) := Bool(false) }
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}
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}
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when (d_flight.opcode === TLMessages.PutFullData || d_flight.opcode === TLMessages.PutPartialData) {
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assert (d.opcode === TLMessages.AccessAck)
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printf(log + " ")
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when (d_flight.opcode === TLMessages.PutFullData) { printf("pf") }
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when (d_flight.opcode === TLMessages.PutPartialData) { printf("pp") }
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printf(" 0x%x - 0x%x\n", d_base, d_base | UIntToOH1(d_size, addressBits))
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}
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when (d_flight.opcode === TLMessages.Get || d_flight.opcode === TLMessages.ArithmeticData || d_flight.opcode === TLMessages.LogicalData) {
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assert (d.opcode === TLMessages.AccessAckData)
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for (i <- 0 until beatBytes) {
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val got = d.data(8*(i+1)-1, 8*i)
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val shadow = Wire(init = d_shadow(i))
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when (d_mask(i)) {
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val d_addr = d_addr_hi << shift | UInt(i)
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printf(log + " ")
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when (d_flight.opcode === TLMessages.Get) { printf("g ") }
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when (d_flight.opcode === TLMessages.ArithmeticData) { printf("a ") }
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when (d_flight.opcode === TLMessages.LogicalData) { printf("l ") }
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printf(" 0x%x := 0x%x", d_addr, got)
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when (!shadow.valid) {
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printf(", undefined (uninitialized or prior overlapping puts)\n")
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} .elsewhen (d_inc(i) =/= d_dec(i)) {
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printf(", undefined (concurrent incomplete puts #%d)\n", d_inc(i) - d_dec(i))
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} .elsewhen (!d_fifo && !d_valid) {
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printf(", undefined (concurrent completed put)\n")
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} .elsewhen (Bool(ignoreErrorData) && d.error) {
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printf(", undefined (error result)\n")
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} .otherwise {
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printf("\n")
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when (shadow.value =/= got) { printf("EXPECTED: 0x%x\n", shadow.value) }
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assert (shadow.value === got)
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}
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}
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}
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}
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when (d_flight.opcode === TLMessages.ArithmeticData || d_flight.opcode === TLMessages.LogicalData) {
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val race = (d_inc zip d_dec) map { case (i, d) => i - d =/= UInt(1) }
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when (d_first) { d_no_race := Bool(true) }
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when ((Cat(race.reverse) & d_mask).orR) { d_no_race := Bool(false) }
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when (d_last) {
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val must_match = d_crc_valid && (d_fifo || (d_valid && d_no_race))
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val error = Bool(ignoreErrorData) && d.error
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printf(log + " crc = 0x%x %d\n", d_crc, must_match.asUInt)
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when (!error && must_match && d_crc =/= d_crc_check) { printf("EXPECTED: 0x%x\n", d_crc_check) }
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assert (!must_match || d_crc === d_crc_check)
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}
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}
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}
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val d_waddr = Mux(wipe, wipeIndex, d_addr_hi)
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for (i <- 0 until beatBytes) {
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val data = Mux(wipe, UInt(0), d_dec_bytes(i) + UInt(1))
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when (dec_bytes_wen(i)) {
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dec_bytes(i).write(d_waddr, data)
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}
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}
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for (i <- 0 until dec_trees.size) {
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val data = Mux(wipe, UInt(0), d_dec_trees(i) + UInt(1))
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when (dec_trees_wen(i)) {
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dec_trees(i).write(d_waddr >> (i+1), data)
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}
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}
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}
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}
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}
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object TLRAMModel
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{
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def apply(log: String = "", ignoreErrorData: Boolean = false)(implicit p: Parameters): TLNode =
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{
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val model = LazyModule(new TLRAMModel(log, ignoreErrorData))
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model.node
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}
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case class MonitorParameters(addressBits: Int, sizeBits: Int)
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class ByteMonitor(params: MonitorParameters) extends GenericParameterizedBundle(params) {
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val valid = Bool()
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val value = UInt(width = 8)
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}
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class FlightMonitor(params: MonitorParameters) extends GenericParameterizedBundle(params) {
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val base = UInt(width = params.addressBits)
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val size = UInt(width = params.sizeBits)
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val opcode = UInt(width = 3)
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}
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}
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