735e4f8ed6
This makes it possible for the bundles to have different widths. Previously, we had to widen all the bundles passing through a node to the widest of all the possibilities. This would mean that if you had two source[] fields, they end up the same.
48 lines
2.6 KiB
Scala
48 lines
2.6 KiB
Scala
// See LICENSE.SiFive for license details.
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package uncore.axi4
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import config._
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import diplomacy._
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object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4EdgeParameters, AXI4Bundle]
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{
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def edgeO(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu)
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def edgeI(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu)
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def bundleO(eo: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(eo.bundle)
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def bundleI(ei: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(ei.bundle)
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def colour = "#00ccff" // bluish
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override def labelI(ei: AXI4EdgeParameters) = (ei.slave.beatBytes * 8).toString
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override def labelO(eo: AXI4EdgeParameters) = (eo.slave.beatBytes * 8).toString
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override def mixO(pd: AXI4MasterPortParameters, node: OutwardNode[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]): AXI4MasterPortParameters =
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pd.copy(masters = pd.masters.map { c => c.copy (nodePath = node +: c.nodePath) })
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override def mixI(pu: AXI4SlavePortParameters, node: InwardNode[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]): AXI4SlavePortParameters =
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pu.copy(slaves = pu.slaves.map { m => m.copy (nodePath = node +: m.nodePath) })
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}
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// Nodes implemented inside modules
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case class AXI4IdentityNode() extends IdentityNode(AXI4Imp)
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case class AXI4MasterNode(portParams: Seq[AXI4MasterPortParameters]) extends SourceNode(AXI4Imp)(portParams)
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case class AXI4SlaveNode(portParams: Seq[AXI4SlavePortParameters]) extends SinkNode(AXI4Imp)(portParams)
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case class AXI4AdapterNode(
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masterFn: AXI4MasterPortParameters => AXI4MasterPortParameters,
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slaveFn: AXI4SlavePortParameters => AXI4SlavePortParameters,
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numPorts: Range.Inclusive = 0 to 999)
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extends AdapterNode(AXI4Imp)(masterFn, slaveFn, numPorts)
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// Nodes passed from an inner module
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case class AXI4OutputNode() extends OutputNode(AXI4Imp)
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case class AXI4InputNode() extends InputNode(AXI4Imp)
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// Nodes used for external ports
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case class AXI4BlindOutputNode(portParams: Seq[AXI4SlavePortParameters]) extends BlindOutputNode(AXI4Imp)(portParams)
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case class AXI4BlindInputNode(portParams: Seq[AXI4MasterPortParameters]) extends BlindInputNode(AXI4Imp)(portParams)
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case class AXI4InternalOutputNode(portParams: Seq[AXI4SlavePortParameters]) extends InternalOutputNode(AXI4Imp)(portParams)
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case class AXI4InternalInputNode(portParams: Seq[AXI4MasterPortParameters]) extends InternalInputNode(AXI4Imp)(portParams)
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