261 lines
7.9 KiB
Scala
261 lines
7.9 KiB
Scala
// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import util.Pow2ClockDivider
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object LFSR16Seed
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{
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def apply(seed: Int): UInt =
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{
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val width = 16
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val lfsr = Reg(init=UInt((seed*0x7231) % 65536, width))
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lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1))
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lfsr
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}
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}
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class RRTestCombinational(val bits: Int, rvalid: Bool => Bool, wready: Bool => Bool) extends Module
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{
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val io = new Bundle {
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val rvalid = Bool(OUTPUT)
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val rready = Bool(INPUT)
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val rdata = UInt(OUTPUT, width = bits)
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val wvalid = Bool(INPUT)
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val wready = Bool(OUTPUT)
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val wdata = UInt(INPUT, width = bits)
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}
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val reg = Reg(UInt(width = bits))
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val rvalid_s = rvalid(io.rready)
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val wready_s = wready(io.wvalid)
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io.rvalid := rvalid_s
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io.wready := wready_s
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io.rdata := reg
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when (io.wvalid && wready_s) { reg := io.wdata }
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}
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object RRTestCombinational
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{
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private var seed = 42
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def always: Bool => Bool = _ => Bool(true)
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def random: Bool => Bool = { ready =>
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seed = seed + 1
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val lfsr = LFSR16Seed(seed)
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val valid = RegInit(Bool(true))
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valid := Mux(valid, !ready, lfsr(0) && lfsr(1))
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valid
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}
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def delay(x: Int): Bool => Bool = { ready =>
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val reg = RegInit(UInt(0, width = log2Ceil(x+1)))
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val valid = reg === UInt(0)
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reg := Mux(ready && valid, UInt(x), Mux(valid, UInt(0), reg - UInt(1)))
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valid
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}
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def combo(bits: Int, rvalid: Bool => Bool, wready: Bool => Bool): RegField = {
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val combo = Module(new RRTestCombinational(bits, rvalid, wready))
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RegField(bits,
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RegReadFn { ready => combo.io.rready := ready; (combo.io.rvalid, combo.io.rdata) },
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RegWriteFn { (valid, data) => combo.io.wvalid := valid; combo.io.wdata := data; combo.io.wready })
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}
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}
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class RRTestRequest(val bits: Int,
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rflow: (Bool, Bool, UInt) => (Bool, Bool, UInt),
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wflow: (Bool, Bool, UInt) => (Bool, Bool, UInt)) extends Module
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{
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val io = new Bundle {
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val rivalid = Bool(INPUT)
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val riready = Bool(OUTPUT)
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val rovalid = Bool(OUTPUT)
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val roready = Bool(INPUT)
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val rdata = UInt(OUTPUT, width = bits)
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val wivalid = Bool(INPUT)
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val wiready = Bool(OUTPUT)
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val wovalid = Bool(OUTPUT)
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val woready = Bool(INPUT)
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val wdata = UInt(INPUT, width = bits)
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}
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val (riready, rovalid, _) = rflow(io.rivalid, io.roready, UInt(0, width = 1))
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val (wiready, wovalid, wdata) = wflow(io.wivalid, io.woready, io.wdata)
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val reg = Reg(UInt(width = bits))
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io.riready := riready
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io.rovalid := rovalid
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io.wiready := wiready
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io.wovalid := wovalid
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val rofire = io.roready && rovalid
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val wofire = io.woready && wovalid
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io.rdata := reg
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when (wofire) { reg := wdata }
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}
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object RRTestRequest
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{
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private var seed = 1231
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def pipe(x: Int): (Bool, Bool, UInt) => (Bool, Bool, UInt) = { (ivalid, oready, idata) =>
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val full = RegInit(Vec.fill(x)(Bool(false)))
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val ready = Wire(Vec(x, Bool()))
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val data = Reg(Vec(x, UInt(width = idata.getWidth)))
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// Construct a classic bubble-filling pipeline
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ready(x-1) := oready || !full(x-1)
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when (ready(0)) { data(0) := idata }
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when (ready(0)) { full(0) := ivalid }
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((ready.init zip ready.tail) zip full.init) foreach { case ((self, next), full) =>
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self := next || !full
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}
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((data.init zip data.tail) zip ready.tail) foreach { case ((prev, self), ready) =>
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when (ready) { self := prev }
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}
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((full.init zip full.tail) zip ready.tail) foreach { case ((prev, self), ready) =>
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when (ready) { self := prev }
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}
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(ready(0), full(x-1), data(x-1))
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}
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def busy: (Bool, Bool, UInt) => (Bool, Bool, UInt) = {
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seed = seed + 1
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(ivalid, oready, idata) => {
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val lfsr = LFSR16Seed(seed)
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val busy = RegInit(Bool(false))
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val data = Reg(UInt(width = idata.getWidth))
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val progress = RegInit(Bool(false))
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val iready = progress && !busy
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val ovalid = progress && busy
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when (progress) {
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busy := Mux(busy, !oready, ivalid)
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progress := Mux(busy, !oready, !ivalid)
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} .otherwise {
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progress := lfsr(0)
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}
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when (ivalid && iready) { data := idata }
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(iready, ovalid, data)
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}
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}
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def request(bits: Int,
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rflow: (Bool, Bool, UInt) => (Bool, Bool, UInt),
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wflow: (Bool, Bool, UInt) => (Bool, Bool, UInt)): RegField = {
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val request = Module(new RRTestRequest(bits, rflow, wflow))
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RegField(bits,
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RegReadFn { (rivalid, roready) =>
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request.io.rivalid := rivalid
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request.io.roready := roready
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(request.io.riready, request.io.rovalid, request.io.rdata) },
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RegWriteFn { (wivalid, woready, wdata) =>
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request.io.wivalid := wivalid
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request.io.woready := woready
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request.io.wdata := wdata
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(request.io.wiready, request.io.wovalid) })
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}
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}
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object RRTest0Map
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{
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import RRTestCombinational._
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def aa(bits: Int) = combo(bits, always, always)
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def ar(bits: Int) = combo(bits, always, random)
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def ad(bits: Int) = combo(bits, always, delay(11))
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def ae(bits: Int) = combo(bits, always, delay(5))
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def ra(bits: Int) = combo(bits, random, always)
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def rr(bits: Int) = combo(bits, random, random)
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def rd(bits: Int) = combo(bits, random, delay(11))
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def re(bits: Int) = combo(bits, random, delay(5))
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def da(bits: Int) = combo(bits, delay(5), always)
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def dr(bits: Int) = combo(bits, delay(5), random)
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def dd(bits: Int) = combo(bits, delay(5), delay(5))
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def de(bits: Int) = combo(bits, delay(5), delay(11))
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def ea(bits: Int) = combo(bits, delay(11), always)
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def er(bits: Int) = combo(bits, delay(11), random)
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def ed(bits: Int) = combo(bits, delay(11), delay(5))
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def ee(bits: Int) = combo(bits, delay(11), delay(11))
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// All fields must respect byte alignment, or else it won't behave like an SRAM
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val map = Seq(
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0 -> Seq(aa(8), ar(8), ad(8), ae(8)),
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1 -> Seq(ra(8), rr(8), rd(8), re(8)),
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2 -> Seq(da(8), dr(8), dd(8), de(8)),
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3 -> Seq(ea(8), er(8), ed(8), ee(8)),
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4 -> Seq(aa(3), ar(5), ad(1), ae(7), ra(2), rr(6), rd(4), re(4)),
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5 -> Seq(da(3), dr(5), dd(1), de(7), ea(2), er(6), ed(4), ee(4)),
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6 -> Seq(aa(8), rr(8), dd(8), ee(8)),
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7 -> Seq(ar(8), rd(8), de(8), ea(8)))
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}
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object RRTest1Map
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{
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import RRTestRequest._
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def pp(bits: Int) = request(bits, pipe(3), pipe(3))
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def pb(bits: Int) = request(bits, pipe(3), busy)
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def bp(bits: Int) = request(bits, busy, pipe(3))
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def bb(bits: Int) = request(bits, busy, busy)
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val map = RRTest0Map.map.take(6) ++ Seq(
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6 -> Seq(pp(8), pb(8), bp(8), bb(8)),
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7 -> Seq(pp(3), pb(5), bp(1), bb(7), pb(5), bp(3), pp(4), bb(4)))
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}
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trait RRTest0Bundle
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{
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}
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trait RRTest0Module extends HasRegMap
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{
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regmap(RRTest0Map.map:_*)
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}
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class RRTest0(address: BigInt) extends TLRegisterRouter(address, 0, 32, 0, 4)(
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new TLRegBundle((), _) with RRTest0Bundle)(
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new TLRegModule((), _, _) with RRTest0Module)
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trait RRTest1Bundle
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{
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}
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trait RRTest1Module extends Module with HasRegMap
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{
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val clocks = Module(new Pow2ClockDivider(2))
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def x(bits: Int) = {
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val field = UInt(width = bits)
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val readCross = Module(new RegisterReadCrossing(field))
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readCross.io.master_clock := clock
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readCross.io.master_reset := reset
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readCross.io.master_allow := Bool(true)
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readCross.io.slave_clock := clocks.io.clock_out
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readCross.io.slave_reset := reset
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readCross.io.slave_allow := Bool(true)
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val writeCross = Module(new RegisterWriteCrossing(field))
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writeCross.io.master_clock := clock
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writeCross.io.master_reset := reset
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writeCross.io.master_allow := Bool(true)
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writeCross.io.slave_clock := clocks.io.clock_out
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writeCross.io.slave_reset := reset
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writeCross.io.slave_allow := Bool(true)
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readCross.io.slave_register := writeCross.io.slave_register
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RegField(bits, readCross.io.master_port, writeCross.io.master_port)
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}
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val map = RRTest1Map.map.drop(1) ++ Seq(0 -> Seq(x(8), x(8), x(8), x(8)))
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regmap(map:_*)
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}
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class RRTest1(address: BigInt) extends TLRegisterRouter(address, 0, 32, 6, 4)(
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new TLRegBundle((), _) with RRTest1Bundle)(
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new TLRegModule((), _, _) with RRTest1Module)
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