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riscv/rocket-chip
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960c2723ab5a2526994ba19dc1b1a37ae31e1ae7
rocket-chip/src/main/scala
T
History
Henry Cook 960c2723ab [tl2] MemoryOpCategories: use def to supply Cat'd consts
2016-11-17 18:42:59 -08:00
..
coreplex
tilelink2 broadcast: make it controlled via Config
2016-11-17 17:26:49 -08:00
diplomacy
tilelink2 Xbar: merge the AddressSets of fractured managers
2016-11-03 22:18:28 -07:00
groundtest
tilelink2 broadcast: make it controlled via Config
2016-11-17 17:26:49 -08:00
junctions
rocketchip: all of the address map now comes from TL2
2016-10-31 11:42:44 -07:00
regmapper
regmapper RegisterCrossing: safe AsyncQueues are overkill here
2016-10-14 18:28:31 -07:00
rocket
[rocket] grant addr bugfix
2016-11-16 18:12:06 -08:00
rocketchip
tilelink2 broadcast: make it controlled via Config
2016-11-17 17:26:49 -08:00
uncore
[tl2] MemoryOpCategories: use def to supply Cat'd consts
2016-11-17 18:42:59 -08:00
unittest
rocket: change connection between rocketchip and coreplex
2016-11-15 18:27:52 -08:00
util
rocket: change connection between rocketchip and coreplex
2016-11-15 18:27:52 -08:00
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