71 lines
2.1 KiB
Scala
71 lines
2.1 KiB
Scala
// See LICENSE for license details.
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package uncore
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import Chisel._
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class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module
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{
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val io = new Bundle {
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val out_fast = Decoupled(data).flip
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val out_slow = Decoupled(data)
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val in_fast = Decoupled(data)
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val in_slow = Decoupled(data).flip
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val clk_slow = Bool(OUTPUT)
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val set_divisor = Valid(Bits(width = 32)).flip
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val divisor = Bits(OUTPUT, 32)
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}
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require(divisor_max >= 8 && divisor_max <= 65536 && isPow2(divisor_max))
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val divisor = Reg(init=UInt(divisor_max-1))
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val d_shadow = Reg(init=UInt(divisor_max-1))
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val hold = Reg(init=UInt(divisor_max/4-1))
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val h_shadow = Reg(init=UInt(divisor_max/4-1))
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when (io.set_divisor.valid) {
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d_shadow := io.set_divisor.bits(log2Up(divisor_max)-1, 0).toUInt
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h_shadow := io.set_divisor.bits(log2Up(divisor_max)-1+16, 16).toUInt
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}
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io.divisor := hold << UInt(16) | divisor
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val count = Reg{UInt(width = log2Up(divisor_max))}
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val myclock = Reg{Bool()}
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count := count + UInt(1)
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val rising = count === (divisor >> UInt(1))
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val falling = count === divisor
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val held = count === (divisor >> UInt(1)) + hold
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when (falling) {
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divisor := d_shadow
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hold := h_shadow
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count := UInt(0)
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myclock := Bool(false)
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}
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when (rising) {
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myclock := Bool(true)
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}
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val in_slow_rdy = Reg(init=Bool(false))
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val out_slow_val = Reg(init=Bool(false))
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val out_slow_bits = Reg(data)
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val fromhost_q = Module(new Queue(data,1))
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fromhost_q.io.enq.valid := rising && (io.in_slow.valid && in_slow_rdy || this.reset)
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fromhost_q.io.enq.bits := io.in_slow.bits
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fromhost_q.io.deq <> io.in_fast
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val tohost_q = Module(new Queue(data,1))
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tohost_q.io.enq <> io.out_fast
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tohost_q.io.deq.ready := rising && io.out_slow.ready && out_slow_val
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when (held) {
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in_slow_rdy := fromhost_q.io.enq.ready
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out_slow_val := tohost_q.io.deq.valid
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out_slow_bits := Mux(this.reset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits)
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}
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io.in_slow.ready := in_slow_rdy
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io.out_slow.valid := out_slow_val
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io.out_slow.bits := out_slow_bits
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io.clk_slow := myclock
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}
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