33 lines
1.1 KiB
Scala
33 lines
1.1 KiB
Scala
package uncore
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import Chisel._
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import junctions._
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import cde.{Parameters, Field}
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class ROMSlave(contents: Seq[Byte])(implicit val p: Parameters) extends Module
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with HasTileLinkParameters
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with HasAddrMapParameters {
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val io = new ClientUncachedTileLinkIO().flip
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val acq = Queue(io.acquire, 1)
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assert(!acq.valid || acq.bits.a_type === Acquire.getType, "unsupported ROMSlave operation")
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val byteWidth = tlDataBits / 8
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val rows = (contents.size + byteWidth - 1)/byteWidth + 1
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val rom = Vec.tabulate(rows) { i =>
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val slice = contents.slice(i*byteWidth, (i+1)*byteWidth)
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UInt(slice.foldRight(BigInt(0)) { case (x,y) => (y << 8) + (x.toInt & 0xFF) }, byteWidth*8)
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}
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val rdata = rom(if (rows == 1) UInt(0) else acq.bits.full_addr()(log2Up(contents.size)-1,log2Up(byteWidth)))
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io.grant.valid := acq.valid
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acq.ready := io.grant.ready
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io.grant.bits := Grant(
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is_builtin_type = Bool(true),
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g_type = acq.bits.getBuiltInGrantType(),
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client_xact_id = acq.bits.client_xact_id,
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manager_xact_id = UInt(0),
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addr_beat = UInt(0),
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data = rdata)
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}
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