145 lines
6.3 KiB
Scala
145 lines
6.3 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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case class SplitterArg[T](newSize: Int, ports: Seq[T])
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case class TLSplitterNode(
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clientFn: SplitterArg[TLClientPortParameters] => Seq[TLClientPortParameters],
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managerFn: SplitterArg[TLManagerPortParameters] => Seq[TLManagerPortParameters],
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numClientPorts: Range.Inclusive = 0 to 999,
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numManagerPorts: Range.Inclusive = 0 to 999)(
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implicit valName: ValName)
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extends TLCustomNode(numClientPorts, numManagerPorts)
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{
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def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
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require (oKnown == 0, s"${name} (a splitter) appears right of a := or :*=; use a :=* instead${lazyModule.line}")
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require (iStars == 0, s"${name} (a splitter) cannot appear left of a :*=; did you mean :=*?${lazyModule.line}")
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(0, iKnown)
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}
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def mapParamsD(n: Int, p: Seq[TLClientPortParameters]): Seq[TLClientPortParameters] = {
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require (p.size == 0 || n % p.size == 0, s"Diplomacy bug; splitter inputs do not divide outputs")
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val out = clientFn(SplitterArg(n, p))
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require (out.size == n, s"${name} created the wrong number of outputs from inputs${lazyModule.line}")
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out
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}
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def mapParamsU(n: Int, p: Seq[TLManagerPortParameters]): Seq[TLManagerPortParameters] = {
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require (n == 0 || p.size % n == 0, s"Diplomacy bug; splitter outputs indivisable by inputs")
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val out = managerFn(SplitterArg(n, p))
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require (out.size == n, s"${name} created the wrong number of inputs from outputs${lazyModule.line}")
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out
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}
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}
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class TLSplitter(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters) extends LazyModule
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{
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val node = TLSplitterNode(
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clientFn = { case SplitterArg(newSize, ports) =>
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if (newSize == 0) Nil else
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Seq.fill(newSize / ports.size) { ports }.flatten
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},
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managerFn = { case SplitterArg(newSize, ports) =>
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if (newSize == 0) Nil else
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ports.grouped(newSize).toList.transpose.map { seq =>
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val fifoIdFactory = TLXbar.relabeler()
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val outputIdRanges = TLXbar.mapOutputIds(seq)
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seq(0).copy(
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minLatency = seq.map(_.minLatency).min,
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endSinkId = outputIdRanges.map(_.map(_.end).getOrElse(0)).max,
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managers = seq.zipWithIndex.flatMap { case (port, i) =>
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require (port.beatBytes == seq(0).beatBytes,
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s"Splitter data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
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val fifoIdMapper = fifoIdFactory()
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port.managers map { manager => manager.copy(
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fifoId = manager.fifoId.map(fifoIdMapper(_))
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)}
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}
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)
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}
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})
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lazy val module = new LazyModuleImp(this) {
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def group[T](x: Seq[T]) =
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if (x.isEmpty) Nil else x.grouped(node.in.size).toList.transpose
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if (node.out.size == node.in.size) {
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(node.in zip node.out) foreach { case ((i, _), (o, _)) => o <> i }
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} else (node.in zip group(node.out)) foreach {
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case ((io_in, edgeIn), seq) =>
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val (io_out, edgesOut) = seq.unzip
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// Grab the port ID mapping
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val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
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// Find a good mask for address decoding
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val port_addrs = edgesOut.map(_.manager.managers.map(_.address).flatten)
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val routingMask = AddressDecoder(port_addrs)
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val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
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val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))
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// We need an intermediate size of bundle with the widest possible identifiers
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val wide_bundle = TLBundleParameters.union(Seq(io_in.params) ++ io_out.map(_.params))
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// Transform input bundle sources (sinks use global namespace on both sides)
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val in = Wire(TLBundle(wide_bundle))
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in.a <> io_in.a
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io_in.d <> in.d
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if (edgeIn.client.anySupportProbe && edgesOut.exists(_.manager.anySupportAcquireB)) {
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in.c <> io_in.c
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in.e <> io_in.e
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io_in.b <> in.b
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} else {
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in.c.valid := Bool(false)
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in.e.valid := Bool(false)
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in.b.ready := Bool(false)
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io_in.c.ready := Bool(true)
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io_in.e.ready := Bool(true)
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io_in.b.valid := Bool(false)
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}
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// Handle size = 1 gracefully (Chisel3 empty range is broken)
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def trim(id: UInt, size: Int) = if (size <= 1) UInt(0) else id(log2Ceil(size)-1, 0)
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// Transform output bundle sinks (sources use global namespace on both sides)
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val out = Wire(Vec(io_out.size, TLBundle(wide_bundle)))
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for (i <- 0 until out.size) {
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val r = outputIdRanges(i)
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io_out(i).a <> out(i).a
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out(i).d <> io_out(i).d
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out(i).d.bits.sink := io_out(i).d.bits.sink | UInt(r.map(_.start).getOrElse(0))
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if (edgesOut(i).manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
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io_out(i).c <> out(i).c
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io_out(i).e <> out(i).e
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out(i).b <> io_out(i).b
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io_out(i).e.bits.sink := trim(out(i).e.bits.sink, r.map(_.size).getOrElse(0))
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} else {
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out(i).c.ready := Bool(false)
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out(i).e.ready := Bool(false)
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out(i).b.valid := Bool(false)
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io_out(i).c.valid := Bool(false)
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io_out(i).e.valid := Bool(false)
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io_out(i).b.ready := Bool(true)
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}
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}
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val requestA = Vec(outputPorts.map { o => o(in.a.bits.address) })
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val requestC = Vec(outputPorts.map { o => o(in.c.bits.address) })
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val requestE = Vec(outputIdRanges.map { o => o.map(_.contains(in.e.bits.sink)).getOrElse(Bool(false)) })
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(out.map(_.a) zip TLXbar.fanout(in.a, requestA)) foreach { case (o, i) => o <> i }
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(out.map(_.c) zip TLXbar.fanout(in.c, requestC)) foreach { case (o, i) => o <> i }
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(out.map(_.e) zip TLXbar.fanout(in.e, requestE)) foreach { case (o, i) => o <> i }
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val beatsB = Vec((out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) })
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val beatsD = Vec((out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) })
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TLArbiter(policy)(in.b, (beatsB zip out.map(_.b)):_*)
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TLArbiter(policy)(in.d, (beatsD zip out.map(_.d)):_*)
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}
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}
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}
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