8bb397a1b9
* Add +permissive/+permissive-off for VCS args This adds guards around Verilog/VCS options for VCS calls with HTIF's new `+permissive`/`+permissive-off` options. This enables HTIF to permissively parse all options inside one of these guards while not erroring on unknonw commands. This is necessary for VCS, unlike with the emulator, as HTIF is giving all commands as opposed to only host and target arguments (like with Verilator/emulator.cc). * Bump riscv-tools for fesvr VCS fix * Bump riscv-rools/riscv-fesvr (VCS stderr fix) Fixes #1266 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
85 lines
2.4 KiB
Plaintext
85 lines
2.4 KiB
Plaintext
#--------------------------------------------------------------------
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# Sources
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#--------------------------------------------------------------------
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# Verilog sources
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bb_vsrcs = \
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$(base_dir)/vsrc/plusarg_reader.v \
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$(base_dir)/vsrc/ClockDivider2.v \
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$(base_dir)/vsrc/ClockDivider3.v \
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$(base_dir)/vsrc/AsyncResetReg.v \
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sim_vsrcs = \
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$(generated_dir)/$(long_name).v \
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$(generated_dir)/$(long_name).behav_srams.v \
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$(base_dir)/vsrc/$(TB).v \
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$(base_dir)/vsrc/SimDTM.v \
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$(base_dir)/vsrc/SimJTAG.v \
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$(bb_vsrcs)
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# C sources
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sim_csrcs = \
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$(base_dir)/csrc/SimDTM.cc \
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$(base_dir)/csrc/SimJTAG.cc \
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$(base_dir)/csrc/remote_bitbang.cc
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#--------------------------------------------------------------------
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# Build Verilog
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#--------------------------------------------------------------------
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verilog: $(sim_vsrcs)
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.PHONY: verilog
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#--------------------------------------------------------------------
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# Build rules
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#--------------------------------------------------------------------
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VCS = vcs -full64
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VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
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+rad +v2k +vcs+lic+wait \
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+vc+list -CC "-I$(VCS_HOME)/include" \
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-CC "-I$(RISCV)/include" \
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-CC "-std=c++11" \
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-CC "-Wl,-rpath,$(RISCV)/lib" \
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$(RISCV)/lib/libfesvr.so \
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-sverilog \
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+incdir+$(generated_dir) \
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+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
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+define+PRINTF_COND=$(TB).printf_cond \
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+define+STOP_COND=!$(TB).reset \
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+define+RANDOMIZE_MEM_INIT \
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+define+RANDOMIZE_REG_INIT \
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+define+RANDOMIZE_GARBAGE_ASSIGN \
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+define+RANDOMIZE_INVALID_ASSIGN \
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+libext+.v \
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#--------------------------------------------------------------------
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# Build the simulator
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#--------------------------------------------------------------------
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simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
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$(simv) : $(sim_vsrcs) $(sim_csrcs)
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cd $(sim_dir) && \
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rm -rf csrc && \
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$(VCS) $(VCS_OPTS) -o $(simv) \
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-debug_pp \
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simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug
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$(simv_debug) : $(sim_vsrcs) $(sim_csrcs)
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cd $(sim_dir) && \
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rm -rf csrc && \
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$(VCS) $(VCS_OPTS) -o $(simv_debug) \
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+define+DEBUG -debug_pp \
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#--------------------------------------------------------------------
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# Run
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#--------------------------------------------------------------------
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seed = $(shell date +%s)
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exec_simv = $(simv) +permissive -q +ntb_random_seed_automatic +permissive-off
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exec_simv_debug = $(simv_debug) +permissive -q +ntb_random_seed_automatic +permissive-off
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