898 lines
28 KiB
Scala
898 lines
28 KiB
Scala
package freechips.rocketchip.devices.debug
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import Chisel._
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// This file was auto-generated from the repository at https://github.com/riscv/riscv-debug-spec.git,
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// 'make chisel'
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object DMI_RegAddrs {
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/* The address of this register will not change in the future, because it
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contains \Fversion. It has changed from version 0.11 of this spec.
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This register reports status for the overall debug module
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as well as the currently selected harts, as defined in \Fhasel.
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Harts are nonexistent if they will never be part of this system, no
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matter how long a user waits. Eg. in a simple single-hart system only
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one hart exists, and all others are nonexistent. Debuggers may assume
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that a system has no harts with indexes higher than the first
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nonexistent one.
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Harts are unavailable if they might exist/become available at a later
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time, or if there are other harts with higher indexes than this one. Eg.
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in a multi-hart system some might temporarily be powered down, or a
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system might support hot-swapping harts. Systems with very large number
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of harts may permanently disable some during manufacturing, leaving
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holes in the otherwise continuous hart index space. In order to let the
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debugger discover all harts, they must show up as unavailable even if
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there is no chance of them ever becoming available.
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*/
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def DMI_DMSTATUS = 0x11
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/* This register controls the overall debug module
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as well as the currently selected harts, as defined in \Fhasel.
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\label{hartsel}
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\index{hartsel}
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Throughout this document we refer to \Fhartsel, which is \Fhartselhi
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combined with \Fhartsello. While the spec allows for 20 \Fhartsel bits,
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an implementation may choose to implement fewer than that. The actual
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width of \Fhartsel is called {\tt HARTSELLEN}. It must be at least 0
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and at most 20. A debugger should discover {\tt HARTSELLEN} by writing
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all ones to \Fhartsel (assuming the maximum size) and reading back the
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value to see which bits were actually set.
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*/
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def DMI_DMCONTROL = 0x10
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/* This register gives information about the hart currently
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selected by \Fhartsel.
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This register is optional. If it is not present it should
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read all-zero.
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If this register is included, the debugger can do more with
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the Program Buffer by writing programs which
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explicitly access the {\tt data} and/or {\tt dscratch}
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registers.
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*/
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def DMI_HARTINFO = 0x12
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/* This register selects which of the 32-bit portion of the hart array mask register
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is accessible in \Rhawindow.
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The hart array mask register provides a mask of all harts controlled by
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the debug module. A hart is part of the currently selected harts if
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the corresponding bit is set in the hart array mask register and
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\Fhasel in \Rdmcontrol is 1, or if the hart is selected by \Fhartsel.
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*/
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def DMI_HAWINDOWSEL = 0x14
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/* This register provides R/W access to a 32-bit portion of the
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hart array mask register.
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The position of the window is determined by \Rhawindowsel. I.e. bit 0
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refers to hart $\Rhawindowsel * 32$, while bit 31 refers to hart
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$\Rhawindowsel * 32 + 31$.
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*/
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def DMI_HAWINDOW = 0x15
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def DMI_ABSTRACTCS = 0x16
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/* Writes to this register cause the corresponding abstract command to be
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executed.
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Writing while an abstract command is executing causes \Fcmderr to be set.
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If \Fcmderr is non-zero, writes to this register are ignored.
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\begin{commentary}
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\Fcmderr inhibits starting a new command to accommodate debuggers
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that, for performance reasons, send several commands to be executed
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in a row without checking \Fcmderr in between. They can safely do
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so and check \Fcmderr at the end without worrying that one command
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failed but then a later command (which might have depended on the
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previous one succeeding) passed.
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\end{commentary}
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*/
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def DMI_COMMAND = 0x17
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/* This register is optional. Including it allows more efficient burst accesses.
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Debugger can attempt to set bits and read them back to determine if the functionality is supported.
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*/
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def DMI_ABSTRACTAUTO = 0x18
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/* When {\tt devtreevalid} is set, reading this register returns bits 31:0
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of the Device Tree address. Reading the other {\tt devtreeaddr}
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registers returns the upper bits of the address.
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When system bus mastering is implemented, this must be an
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address that can be used with the System Bus Access module. Otherwise,
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this must be an address that can be used to access the
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Device Tree from the hart with ID 0.
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If {\tt devtreevalid} is 0, then the {\tt devtreeaddr} registers
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hold identifier information which is not
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further specified in this document.
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The Device Tree itself is described in the RISC-V Privileged
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Specification.
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*/
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def DMI_DEVTREEADDR0 = 0x19
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def DMI_DEVTREEADDR1 = 0x1a
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def DMI_DEVTREEADDR2 = 0x1b
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def DMI_DEVTREEADDR3 = 0x1c
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/* If there is more than one DM accessible on this DMI, this register
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contains the base address of the next one in the chain, or 0 if this is
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the last one in the chain.
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*/
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def DMI_NEXTDM = 0x1d
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/* \Rdatazero through \Rdataeleven are basic read/write registers that may
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be read or changed by abstract commands. \Fdatacount indicates how many
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of them are implemented, starting at \Rsbdatazero, counting up.
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Table~\ref{tab:datareg} shows how abstract commands use these
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registers.
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Accessing these registers while an abstract command is executing causes
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\Fcmderr to be set.
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Attempts to write them while \Fbusy is set does not change their value.
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The values in these registers may not be preserved after an abstract
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command is executed. The only guarantees on their contents are the ones
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offered by the command in question. If the command fails, no
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assumptions can be made about the contents of these registers.
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*/
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def DMI_DATA0 = 0x04
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def DMI_DATA11 = 0x0f
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/* \Rprogbufzero through \Rprogbuffifteen provide read/write access to the
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optional program buffer. \Fprogbufsize indicates how many of them are
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implemented starting at \Rprogbufzero, counting up.
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Accessing these registers while an abstract command is executing causes
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\Fcmderr to be set.
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Attempts to write them while \Fbusy is set does not change their value.
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*/
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def DMI_PROGBUF0 = 0x20
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def DMI_PROGBUF15 = 0x2f
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/* This register serves as a 32-bit serial port to the authentication
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module.
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When \Fauthbusy is clear, the debugger can communicate with the
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authentication module by reading or writing this register. There is no
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separate mechanism to signal overflow/underflow.
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*/
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def DMI_AUTHDATA = 0x30
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/* Each bit in this read-only register indicates whether one specific hart
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is halted or not.
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The LSB reflects the halt status of hart \{hartsel[19:5],5'h0\}, and the
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MSB reflects halt status of hart \{hartsel[19:5],5'h1f\}.
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*/
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def DMI_HALTSUM0 = 0x40
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/* Each bit in this read-only register indicates whether any of a group of
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harts is halted or not.
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This register may not be present in systems with fewer than
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33 harts.
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The LSB reflects the halt status of harts \{hartsel[19:10],10'h0\}
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through \{hartsel[19:10],10'h1f\}.
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The MSB reflects the halt status of harts \{hartsel[19:10],10'h3e0\}
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through \{hartsel[19:10],10'h3ff\}.
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*/
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def DMI_HALTSUM1 = 0x13
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/* Each bit in this read-only register indicates whether any of a group of
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harts is halted or not.
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This register may not be present in systems with fewer than
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1025 harts.
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The LSB reflects the halt status of harts \{hartsel[19:15],15'h0\}
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through \{hartsel[19:15],15'h3ff\}.
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The MSB reflects the halt status of harts \{hartsel[19:15],15'h7c00\}
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through \{hartsel[19:15],15'h7fff\}.
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*/
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def DMI_HALTSUM2 = 0x34
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/* Each bit in this read-only register indicates whether any of a group of
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harts is halted or not.
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This register may not be present in systems with fewer than
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32769 harts.
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The LSB reflects the halt status of harts 20'h0 through 20'h7fff.
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The MSB reflects the halt status of harts 20'hf8000 through 20'hfffff.
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*/
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def DMI_HALTSUM3 = 0x35
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/* If \Fsbasize is less than 97, then this register is not present.
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When the system bus master is busy, writes to this register will set
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\Fsbbusyerror and don't do anything else.
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*/
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def DMI_SBADDRESS3 = 0x37
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def DMI_SBCS = 0x38
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/* If \Fsbasize is 0, then this register is not present.
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When the system bus master is busy, writes to this register will set
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\Fsbbusyerror and don't do anything else.
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\begin{steps}{If \Fsberror is 0, \Fsbbusyerror is 0, and \Fsbreadonaddr
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is set then writes to this register start the following:}
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\item Set \Fsbbusy.
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\item Perform a bus read from the new value of {\tt sbaddress}.
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\item If the read succeeded and \Fsbautoincrement is set, increment
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{\tt sbaddress}.
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\item Clear \Fsbbusy.
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\end{steps}
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*/
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def DMI_SBADDRESS0 = 0x39
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/* If \Fsbasize is less than 33, then this register is not present.
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When the system bus master is busy, writes to this register will set
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\Fsbbusyerror and don't do anything else.
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*/
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def DMI_SBADDRESS1 = 0x3a
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/* If \Fsbasize is less than 65, then this register is not present.
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When the system bus master is busy, writes to this register will set
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\Fsbbusyerror and don't do anything else.
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*/
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def DMI_SBADDRESS2 = 0x3b
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/* If all of the {\tt sbaccess} bits in \Rsbcs are 0, then this register
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is not present.
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Any successful system bus read updates the data in this register.
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If \Fsberror or \Fsbbusyerror both aren't 0 then accesses do nothing.
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If the bus master is busy then accesses set \Fsbbusyerror, and don't do
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anything else.
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\begin{steps}{Writes to this register start the following:}
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\item Set \Fsbbusy.
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\item Perform a bus write of the new value of {\tt sbdata} to {\tt sbaddress}.
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\item If the write succeeded and \Fsbautoincrement is set,
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increment {\tt sbaddress}.
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\item Clear \Fsbbusy.
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\end{steps}
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\begin{steps}{Reads from this register start the following:}
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\item ``Return'' the data.
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\item Set \Fsbbusy.
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\item If \Fsbautoincrement is set, increment {\tt sbaddress}.
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\item If \Fsbreadondata is set, perform another system bus read.
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\item Clear \Fsbbusy.
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\end{steps}
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Only \Rsbdatazero has this behavior. The other {\tt sbdata} registers
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have no side effects. On systems that have buses wider than 32 bits, a
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debugger should access \Rsbdatazero after accessing the other {\tt
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sbdata} registers.
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*/
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def DMI_SBDATA0 = 0x3c
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/* If \Fsbaccesssixtyfour and \Fsbaccessonetwentyeight are 0, then this
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register is not present.
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If the bus master is busy then accesses set \Fsbbusyerror, and don't do
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anything else.
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*/
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def DMI_SBDATA1 = 0x3d
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/* This register only exists if \Fsbaccessonetwentyeight is 1.
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If the bus master is busy then accesses set \Fsbbusyerror, and don't do
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anything else.
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*/
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def DMI_SBDATA2 = 0x3e
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/* This register only exists if \Fsbaccessonetwentyeight is 1.
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If the bus master is busy then accesses set \Fsbbusyerror, and don't do
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anything else.
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*/
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def DMI_SBDATA3 = 0x3f
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}
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class DMSTATUSFields extends Bundle {
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val reserved0 = UInt(9.W)
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/* If 1, then there is an implicit {\tt ebreak} instruction at the
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non-existent word immediately after the Program Buffer. This saves
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the debugger from having to write the {\tt ebreak} itself, and
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allows the Program Buffer to be one word smaller.
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This must be 1 when \Fprogbufsize is 1.
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*/
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val impebreak = Bool()
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val reserved1 = UInt(2.W)
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/* This field is 1 when all currently selected harts have been reset but the reset has not been acknowledged.
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*/
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val allhavereset = Bool()
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/* This field is 1 when any currently selected hart has been reset but the reset has not been acknowledged.
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*/
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val anyhavereset = Bool()
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/* This field is 1 when all currently selected harts have acknowledged
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the previous resume request.
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*/
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val allresumeack = Bool()
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/* This field is 1 when any currently selected hart has acknowledged
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the previous resume request.
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*/
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val anyresumeack = Bool()
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/* This field is 1 when all currently selected harts do not exist in this system.
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*/
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val allnonexistent = Bool()
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/* This field is 1 when any currently selected hart does not exist in this system.
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*/
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val anynonexistent = Bool()
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/* This field is 1 when all currently selected harts are unavailable.
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*/
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val allunavail = Bool()
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/* This field is 1 when any currently selected hart is unavailable.
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*/
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val anyunavail = Bool()
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/* This field is 1 when all currently selected harts are running.
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*/
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val allrunning = Bool()
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/* This field is 1 when any currently selected hart is running.
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*/
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val anyrunning = Bool()
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/* This field is 1 when all currently selected harts are halted.
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*/
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val allhalted = Bool()
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/* This field is 1 when any currently selected hart is halted.
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*/
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val anyhalted = Bool()
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/* 0 when authentication is required before using the DM. 1 when the
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authentication check has passed. On components that don't implement
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authentication, this bit must be preset as 1.
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*/
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val authenticated = Bool()
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/* 0: The authentication module is ready to process the next
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read/write to \Rauthdata.
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1: The authentication module is busy. Accessing \Rauthdata results
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in unspecified behavior.
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\Fauthbusy only becomes set in immediate response to an access to
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\Rauthdata.
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*/
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val authbusy = Bool()
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val reserved2 = UInt(1.W)
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/* 0: \Rdevtreeaddrzero--\Rdevtreeaddrthree hold information which
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is not relevant to the Device Tree.
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1: \Rdevtreeaddrzero--\Rdevtreeaddrthree registers hold the address of the
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Device Tree.
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*/
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val devtreevalid = Bool()
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/* 0: There is no Debug Module present.
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1: There is a Debug Module and it conforms to version 0.11 of this
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specification.
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2: There is a Debug Module and it conforms to version 0.13 of this
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specification.
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15: There is a Debug Module but it does not conform to any
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available version of this spec.
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*/
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val version = UInt(4.W)
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}
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class DMCONTROLFields extends Bundle {
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/* Writes the halt request bit for all currently selected harts.
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When set to 1, each selected hart will halt if it is not currently
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halted.
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Writing 1 or 0 has no effect on a hart which is already halted, but
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the bit must be cleared to 0 before the hart is resumed.
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Writes apply to the new value of \Fhartsel and \Fhasel.
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*/
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val haltreq = Bool()
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/* Writes the resume request bit for all currently selected harts.
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When set to 1, each selected hart will resume if it is currently
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halted.
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The resume request bit is ignored while the halt request bit is
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set.
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Writes apply to the new value of \Fhartsel and \Fhasel.
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*/
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val resumereq = Bool()
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/* This optional field writes the reset bit for all the currently
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selected harts. To perform a reset the debugger writes 1, and then
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writes 0 to deassert the reset signal.
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If this feature is not implemented, the bit always stays 0, so
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after writing 1 the debugger can read the register back to see if
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the feature is supported.
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Writes apply to the new value of \Fhartsel and \Fhasel.
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*/
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val hartreset = Bool()
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/* Writing 1 to this bit clears the {\tt havereset} bits for
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any selected harts.
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Writes apply to the new value of \Fhartsel and \Fhasel.
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*/
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val ackhavereset = Bool()
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val reserved0 = UInt(1.W)
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/* Selects the definition of currently selected harts.
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0: There is a single currently selected hart, that selected by \Fhartsel.
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1: There may be multiple currently selected harts -- that selected by \Fhartsel,
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plus those selected by the hart array mask register.
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An implementation which does not implement the hart array mask register
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should tie this field to 0. A debugger which wishes to use the hart array
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mask register feature should set this bit and read back to see if the functionality
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is supported.
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*/
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val hasel = Bool()
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/* The low 10 bits of \Fhartsel: the DM-specific index of the hart to
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select. This hart is always part of the currently selected harts.
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*/
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val hartsello = UInt(10.W)
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/* The high 10 bits of \Fhartsel: the DM-specific index of the hart to
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select. This hart is always part of the currently selected harts.
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*/
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val hartselhi = UInt(10.W)
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val reserved1 = UInt(4.W)
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/* This bit controls the reset signal from the DM to the rest of the
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system. The signal should reset every part of the system, including
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every hart, except for the DM and any logic required to access the
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DM.
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To perform a system reset the debugger writes 1,
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and then writes 0
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to deassert the reset.
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*/
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val ndmreset = Bool()
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/* This bit serves as a reset signal for the Debug Module itself.
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0: The module's state, including authentication mechanism,
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takes its reset values (the \Fdmactive bit is the only bit which can
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be written to something other than its reset value).
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1: The module functions normally.
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No other mechanism should exist that may result in resetting the
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Debug Module after power up, including the platform's system reset
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or Debug Transport reset signals.
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A debugger may pulse this bit low to get the debug module into a
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known state.
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Implementations may use this bit to aid debugging, for example by
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preventing the Debug Module from being power gated while debugging
|
|
is active.
|
|
*/
|
|
val dmactive = Bool()
|
|
|
|
}
|
|
|
|
class HARTINFOFields extends Bundle {
|
|
|
|
val reserved0 = UInt(8.W)
|
|
|
|
/* Number of {\tt dscratch} registers available for the debugger
|
|
to use during program buffer execution, starting from \Rdscratchzero.
|
|
The debugger can make no assumptions about the contents of these
|
|
registers between commands.
|
|
*/
|
|
val nscratch = UInt(4.W)
|
|
|
|
val reserved1 = UInt(3.W)
|
|
|
|
/* 0: The {\tt data} registers are shadowed in the hart by CSR
|
|
registers. Each CSR register is XLEN bits in size, and corresponds
|
|
to a single argument, per Table~\ref{tab:datareg}.
|
|
|
|
1: The {\tt data} registers are shadowed in the hart's memory map.
|
|
Each register takes up 4 bytes in the memory map.
|
|
*/
|
|
val dataaccess = Bool()
|
|
|
|
/* If \Fdataaccess is 0: Number of CSR registers dedicated to
|
|
shadowing the {\tt data} registers.
|
|
|
|
If \Fdataaccess is 1: Number of 32-bit words in the memory map
|
|
dedicated to shadowing the {\tt data} registers.
|
|
|
|
Since there are at most 12 {\tt data} registers, the value in this
|
|
register must be 12 or smaller.
|
|
*/
|
|
val datasize = UInt(4.W)
|
|
|
|
/* If \Fdataaccess is 0: The number of the first CSR dedicated to
|
|
shadowing the {\tt data} registers.
|
|
|
|
If \Fdataaccess is 1: Signed address of RAM where the {\tt data}
|
|
registers are shadowed, to be used to access relative to \Rzero.
|
|
*/
|
|
val dataaddr = UInt(12.W)
|
|
|
|
}
|
|
|
|
class HAWINDOWSELFields extends Bundle {
|
|
|
|
val reserved0 = UInt(17.W)
|
|
|
|
val hawindowsel = UInt(15.W)
|
|
|
|
}
|
|
|
|
class HAWINDOWFields extends Bundle {
|
|
|
|
val maskdata = UInt(32.W)
|
|
|
|
}
|
|
|
|
class ABSTRACTCSFields extends Bundle {
|
|
|
|
val reserved0 = UInt(3.W)
|
|
|
|
/* Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16.
|
|
*/
|
|
val progbufsize = UInt(5.W)
|
|
|
|
val reserved1 = UInt(11.W)
|
|
|
|
/* 1: An abstract command is currently being executed.
|
|
|
|
This bit is set as soon as \Rcommand is written, and is
|
|
not cleared until that command has completed.
|
|
*/
|
|
val busy = Bool()
|
|
|
|
val reserved2 = UInt(1.W)
|
|
|
|
/* Gets set if an abstract command fails. The bits in this field remain set until
|
|
they are cleared by writing 1 to them. No abstract command is
|
|
started until the value is reset to 0.
|
|
|
|
0 (none): No error.
|
|
|
|
1 (busy): An abstract command was executing while \Rcommand,
|
|
\Rabstractcs, \Rabstractauto was written, or when one
|
|
of the {\tt data} or {\tt progbuf} registers was read or written.
|
|
|
|
2 (not supported): The requested command is not supported. A
|
|
command that is not supported while the hart is running may be
|
|
supported when it is halted.
|
|
|
|
3 (exception): An exception occurred while executing the command
|
|
(eg. while executing the Program Buffer).
|
|
|
|
4 (halt/resume): An abstract command couldn't execute because the
|
|
hart wasn't in the expected state (running/halted).
|
|
|
|
7 (other): The command failed for another reason.
|
|
*/
|
|
val cmderr = UInt(3.W)
|
|
|
|
val reserved3 = UInt(4.W)
|
|
|
|
/* Number of {\tt data} registers that are implemented as part of the
|
|
abstract command interface. Valid sizes are 0 - 12.
|
|
*/
|
|
val datacount = UInt(4.W)
|
|
|
|
}
|
|
|
|
class COMMANDFields extends Bundle {
|
|
|
|
/* The type determines the overall functionality of this
|
|
abstract command.
|
|
*/
|
|
val cmdtype = UInt(8.W)
|
|
|
|
/* This field is interpreted in a command-specific manner,
|
|
described for each abstract command.
|
|
*/
|
|
val control = UInt(24.W)
|
|
|
|
}
|
|
|
|
class ABSTRACTAUTOFields extends Bundle {
|
|
|
|
/* When a bit in this field is 1, read or write accesses to the corresponding {\tt progbuf} word
|
|
cause the command in \Rcommand to be executed again.
|
|
*/
|
|
val autoexecprogbuf = UInt(16.W)
|
|
|
|
val reserved0 = UInt(4.W)
|
|
|
|
/* When a bit in this field is 1, read or write accesses to the corresponding {\tt data} word
|
|
cause the command in \Rcommand to be executed again.
|
|
*/
|
|
val autoexecdata = UInt(12.W)
|
|
|
|
}
|
|
|
|
class DEVTREEADDR0Fields extends Bundle {
|
|
|
|
val addr = UInt(32.W)
|
|
|
|
}
|
|
|
|
class NEXTDMFields extends Bundle {
|
|
|
|
val addr = UInt(32.W)
|
|
|
|
}
|
|
|
|
class DATA0Fields extends Bundle {
|
|
|
|
val data = UInt(32.W)
|
|
|
|
}
|
|
|
|
class PROGBUF0Fields extends Bundle {
|
|
|
|
val data = UInt(32.W)
|
|
|
|
}
|
|
|
|
class AUTHDATAFields extends Bundle {
|
|
|
|
val data = UInt(32.W)
|
|
|
|
}
|
|
|
|
class HALTSUM0Fields extends Bundle {
|
|
|
|
val haltsum0 = UInt(32.W)
|
|
|
|
}
|
|
|
|
class HALTSUM1Fields extends Bundle {
|
|
|
|
val haltsum1 = UInt(32.W)
|
|
|
|
}
|
|
|
|
class HALTSUM2Fields extends Bundle {
|
|
|
|
val haltsum2 = UInt(32.W)
|
|
|
|
}
|
|
|
|
class HALTSUM3Fields extends Bundle {
|
|
|
|
val haltsum3 = UInt(32.W)
|
|
|
|
}
|
|
|
|
class SBADDRESS3Fields extends Bundle {
|
|
|
|
/* Accesses bits 127:96 of the physical address in {\tt sbaddress} (if
|
|
the system address bus is that wide).
|
|
*/
|
|
val address = UInt(32.W)
|
|
|
|
}
|
|
|
|
class SBCSFields extends Bundle {
|
|
|
|
/* 0: The System Bus interface conforms to mainline drafts of this
|
|
spec older than 1 January, 2018.
|
|
|
|
1: The System Bus interface conforms to this version of the spec.
|
|
|
|
Other values are reserved for future versions.
|
|
*/
|
|
val sbversion = UInt(3.W)
|
|
|
|
val reserved0 = UInt(6.W)
|
|
|
|
/* Set when the debugger attempts to read data while a read is in
|
|
progress, or when the debugger initiates a new access while one is
|
|
already in progress (while \Fsbbusy is set). It remains set until
|
|
it's explicitly cleared by the debugger.
|
|
|
|
While this field is non-zero, no more system bus accesses can be
|
|
initiated by the debug module.
|
|
*/
|
|
val sbbusyerror = Bool()
|
|
|
|
/* When 1, indicates the system bus master is busy. (Whether the
|
|
system bus itself is busy is related, but not the same thing.) This
|
|
bit goes high immediately when a read or write is requested for any
|
|
reason, and does not go low until the access is fully completed.
|
|
|
|
To avoid race conditions, debuggers must not try to clear \Fsberror
|
|
until they read \Fsbbusy as 0.
|
|
*/
|
|
val sbbusy = Bool()
|
|
|
|
/* When 1, every write to \Rsbaddresszero automatically triggers a
|
|
system bus read at the new address.
|
|
*/
|
|
val sbreadonaddr = Bool()
|
|
|
|
/* Select the access size to use for system bus accesses.
|
|
|
|
0: 8-bit
|
|
|
|
1: 16-bit
|
|
|
|
2: 32-bit
|
|
|
|
3: 64-bit
|
|
|
|
4: 128-bit
|
|
|
|
If \Fsbaccess has an unsupported value when the DM starts a bus
|
|
access, the access is not performed and \Fsberror is set to 3.
|
|
*/
|
|
val sbaccess = UInt(3.W)
|
|
|
|
/* When 1, {\tt sbaddress} is incremented by the access size (in
|
|
bytes) selected in \Fsbaccess after every system bus access.
|
|
*/
|
|
val sbautoincrement = Bool()
|
|
|
|
/* When 1, every read from \Rsbdatazero automatically triggers a
|
|
system bus read at the (possibly auto-incremented) address.
|
|
*/
|
|
val sbreadondata = Bool()
|
|
|
|
/* When the debug module's system bus
|
|
master causes a bus error, this field gets set. The bits in this
|
|
field remain set until they are cleared by writing 1 to them.
|
|
While this field is non-zero, no more system bus accesses can be
|
|
initiated by the debug module.
|
|
|
|
0: There was no bus error.
|
|
|
|
1: There was a timeout.
|
|
|
|
2: A bad address was accessed.
|
|
|
|
3: There was some other error (eg. alignment).
|
|
*/
|
|
val sberror = UInt(3.W)
|
|
|
|
/* Width of system bus addresses in bits. (0 indicates there is no bus
|
|
access support.)
|
|
*/
|
|
val sbasize = UInt(7.W)
|
|
|
|
/* 1 when 128-bit system bus accesses are supported.
|
|
*/
|
|
val sbaccess128 = Bool()
|
|
|
|
/* 1 when 64-bit system bus accesses are supported.
|
|
*/
|
|
val sbaccess64 = Bool()
|
|
|
|
/* 1 when 32-bit system bus accesses are supported.
|
|
*/
|
|
val sbaccess32 = Bool()
|
|
|
|
/* 1 when 16-bit system bus accesses are supported.
|
|
*/
|
|
val sbaccess16 = Bool()
|
|
|
|
/* 1 when 8-bit system bus accesses are supported.
|
|
*/
|
|
val sbaccess8 = Bool()
|
|
|
|
}
|
|
|
|
class SBADDRESS0Fields extends Bundle {
|
|
|
|
/* Accesses bits 31:0 of the physical address in {\tt sbaddress}.
|
|
*/
|
|
val address = UInt(32.W)
|
|
|
|
}
|
|
|
|
class SBADDRESS1Fields extends Bundle {
|
|
|
|
/* Accesses bits 63:32 of the physical address in {\tt sbaddress} (if
|
|
the system address bus is that wide).
|
|
*/
|
|
val address = UInt(32.W)
|
|
|
|
}
|
|
|
|
class SBADDRESS2Fields extends Bundle {
|
|
|
|
/* Accesses bits 95:64 of the physical address in {\tt sbaddress} (if
|
|
the system address bus is that wide).
|
|
*/
|
|
val address = UInt(32.W)
|
|
|
|
}
|
|
|
|
class SBDATA0Fields extends Bundle {
|
|
|
|
/* Accesses bits 31:0 of {\tt sbdata}.
|
|
*/
|
|
val data = UInt(32.W)
|
|
|
|
}
|
|
|
|
class SBDATA1Fields extends Bundle {
|
|
|
|
/* Accesses bits 63:32 of {\tt sbdata} (if the system bus is that
|
|
wide).
|
|
*/
|
|
val data = UInt(32.W)
|
|
|
|
}
|
|
|
|
class SBDATA2Fields extends Bundle {
|
|
|
|
/* Accesses bits 95:64 of {\tt sbdata} (if the system bus is that
|
|
wide).
|
|
*/
|
|
val data = UInt(32.W)
|
|
|
|
}
|
|
|
|
class SBDATA3Fields extends Bundle {
|
|
|
|
/* Accesses bits 127:96 of {\tt sbdata} (if the system bus is that
|
|
wide).
|
|
*/
|
|
val data = UInt(32.W)
|
|
|
|
}
|
|
|