4c595d175c
* Refactors package hierarchy. Additionally: - Removes legacy ground tests and configs - Removes legacy bus protocol implementations - Removes NTiles - Adds devices package - Adds more functions to util package
36 lines
1.1 KiB
Scala
36 lines
1.1 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.ahb
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import Chisel._
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import freechips.rocketchip.util.GenericParameterizedBundle
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abstract class AHBBundleBase(params: AHBBundleParameters) extends GenericParameterizedBundle(params)
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// Signal directions are from the master's point-of-view
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class AHBBundle(params: AHBBundleParameters) extends AHBBundleBase(params)
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{
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// Flow control signals from the master
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val hmastlock = Bool(OUTPUT)
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val htrans = UInt(OUTPUT, width = params.transBits)
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val hsel = Bool(OUTPUT)
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val hready = Bool(OUTPUT) // on a master, drive this from readyout
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// Payload signals
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val hwrite = Bool(OUTPUT)
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val haddr = UInt(OUTPUT, width = params.addrBits)
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val hsize = UInt(OUTPUT, width = params.sizeBits)
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val hburst = UInt(OUTPUT, width = params.burstBits)
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val hprot = UInt(OUTPUT, width = params.protBits)
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val hwdata = UInt(OUTPUT, width = params.dataBits)
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val hreadyout = Bool(INPUT)
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val hresp = Bool(INPUT)
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val hrdata = UInt(INPUT, width = params.dataBits)
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}
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object AHBBundle
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{
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def apply(params: AHBBundleParameters) = new AHBBundle(params)
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}
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