b8098d18be
The reason for the :=? operator was for when you have an adapter chain whose direction of cardinality you could not know. We used explicit directives to tell these compositions which way to go. Unfortunately, that makes the API leaky. You think the chain of adapters is just one adapter, but you have to use strange Cardinality scopes to use it. That's just bad. The new :*=* just automagically figures it out from the graph.
62 lines
1.9 KiB
Scala
62 lines
1.9 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.config.Field
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case class PeripheryBusParams(
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beatBytes: Int,
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blockBytes: Int,
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masterBuffering: BufferParams = BufferParams.default,
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slaveBuffering: BufferParams = BufferParams.none,
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arithmetic: Boolean = true,
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frequency: BigInt = BigInt(100000000) // 100 MHz as default bus frequency
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) extends TLBusParams {
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}
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case object PeripheryBusKey extends Field[PeripheryBusParams]
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class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "PeripheryBus") {
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def toFixedWidthSingleBeatSlave(widthBytes: Int) = {
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TLFragmenter(widthBytes, params.blockBytes) := outwardWWNode
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}
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def toLargeBurstSlave(maxXferBytes: Int) = {
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TLFragmenter(params.beatBytes, maxXferBytes) := outwardBufNode
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}
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val fromSystemBus: TLInwardNode = {
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val atomics = LazyModule(new TLAtomicAutomata(arithmetic = params.arithmetic))
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xbar.node :*= TLBuffer(params.masterBuffering) :*= atomics.node
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}
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def toTile(name: Option[String] = None)(gen: Parameters => TLInwardNode) {
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this {
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LazyScope(s"${busName}ToTile${name.getOrElse("")}") {
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FlipRendering { implicit p =>
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gen(p) :*= outwardNode
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}
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}
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}
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}
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}
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/** Provides buses that serve as attachment points,
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* for use in traits that connect individual devices or external ports.
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*/
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trait HasPeripheryBus extends HasSystemBus {
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private val pbusParams = p(PeripheryBusKey)
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val pbusBeatBytes = pbusParams.beatBytes
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val pbus = LazyModule(new PeripheryBus(pbusParams))
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// The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
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pbus.fromSystemBus :*= sbus.toPeripheryBus()
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}
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