25 lines
847 B
Scala
25 lines
847 B
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.subsystem
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import Chisel._
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import freechips.rocketchip.diplomacy.{LazyModuleImp, DTSTimebase}
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import freechips.rocketchip.devices.tilelink.HasPeripheryCLINT
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trait HasRTCModuleImp extends LazyModuleImp {
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val outer: HasPeripheryCLINT
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private val pbusFreq = outer.p(PeripheryBusKey).frequency
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private val rtcFreq = outer.p(DTSTimebase)
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private val internalPeriod: BigInt = pbusFreq / rtcFreq
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// check whether pbusFreq >= rtcFreq
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require(internalPeriod > 0)
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// check wehther the integer division is within 5% of the real division
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require((pbusFreq - rtcFreq * internalPeriod) * 100 / pbusFreq <= 5)
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// Use the static period to toggle the RTC
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val (_, int_rtc_tick) = Counter(true.B, internalPeriod.toInt)
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outer.clint.module.io.rtcTick := int_rtc_tick
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}
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