54 lines
1.8 KiB
Scala
54 lines
1.8 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.subsystem
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import Chisel._
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import chisel3.experimental.dontTouch
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.tile.{BaseTile, TileParams, SharedMemoryTLEdge, HasExternallyDrivenTileConstants}
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import freechips.rocketchip.util._
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class ClockedTileInputs(implicit val p: Parameters) extends ParameterizedBundle
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with HasExternallyDrivenTileConstants
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with Clocked
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trait HasTiles extends HasSystemBus {
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val tiles: Seq[BaseTile]
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protected def tileParams: Seq[TileParams] = tiles.map(_.tileParams)
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def nTiles: Int = tileParams.size
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def hartIdList: Seq[Int] = tileParams.map(_.hartId)
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def localIntCounts: Seq[Int] = tileParams.map(_.core.nLocalInterrupts)
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}
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trait HasTilesBundle {
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val tile_inputs: Vec[ClockedTileInputs]
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}
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trait HasTilesModuleImp extends LazyModuleImp
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with HasTilesBundle
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with HasResetVectorWire {
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val outer: HasTiles
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def resetVectorBits: Int = {
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// Consider using the minimum over all widths, rather than enforcing homogeneity
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val vectors = outer.tiles.map(_.module.constants.reset_vector)
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require(vectors.tail.forall(_.getWidth == vectors.head.getWidth))
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vectors.head.getWidth
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}
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val tile_inputs = dontTouch(Wire(Vec(outer.nTiles, new ClockedTileInputs()(p.alterPartial {
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case SharedMemoryTLEdge => outer.sharedMemoryTLEdge
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})))) // dontTouch keeps constant prop from sucking these signals into the tile
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// Unconditionally wire up the non-diplomatic tile inputs
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outer.tiles.map(_.module).zip(tile_inputs).foreach { case(tile, wire) =>
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tile.clock := wire.clock
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tile.reset := wire.reset
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tile.constants.hartid := wire.hartid
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tile.constants.reset_vector := wire.reset_vector
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}
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}
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