312 lines
10 KiB
Scala
312 lines
10 KiB
Scala
// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.rocket
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import Chisel._
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import Chisel.ImplicitConversions._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.subsystem.CacheBlockBytes
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import freechips.rocketchip.tile._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util.property._
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import chisel3.internal.sourceinfo.SourceInfo
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import scala.collection.mutable.ListBuffer
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class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
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val addr = UInt(width = vpnBits)
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}
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class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {
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val ae = Bool()
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val pte = new PTE
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val level = UInt(width = log2Ceil(pgLevels))
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val homogeneous = Bool()
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}
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class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p)
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with HasCoreParameters {
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val req = Decoupled(new PTWReq)
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val resp = Valid(new PTWResp).flip
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val ptbr = new PTBR().asInput
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val status = new MStatus().asInput
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val pmp = Vec(nPMPs, new PMP).asInput
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}
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class PTWPerfEvents extends Bundle {
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val l2miss = Bool()
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}
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class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p)
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with HasCoreParameters {
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val ptbr = new PTBR().asInput
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val sfence = Valid(new SFenceReq).flip
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val status = new MStatus().asInput
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val pmp = Vec(nPMPs, new PMP).asInput
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val perf = new PTWPerfEvents().asOutput
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}
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class PTE(implicit p: Parameters) extends CoreBundle()(p) {
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val ppn = UInt(width = 54)
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val reserved_for_software = Bits(width = 2)
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val d = Bool()
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val a = Bool()
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val g = Bool()
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val u = Bool()
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val x = Bool()
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val w = Bool()
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val r = Bool()
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val v = Bool()
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def table(dummy: Int = 0) = v && !r && !w && !x
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def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a
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def ur(dummy: Int = 0) = sr() && u
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def uw(dummy: Int = 0) = sw() && u
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def ux(dummy: Int = 0) = sx() && u
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def sr(dummy: Int = 0) = leaf() && r
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def sw(dummy: Int = 0) = leaf() && w && d
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def sx(dummy: Int = 0) = leaf() && x
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}
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class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val requestor = Vec(n, new TLBPTWIO).flip
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val mem = new HellaCacheIO
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val dpath = new DatapathPTWIO
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}
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val s_ready :: s_req :: s_wait1 :: s_wait2 :: Nil = Enum(UInt(), 4)
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val state = Reg(init=s_ready)
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val count = Reg(UInt(width = log2Up(pgLevels)))
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val s1_kill = Reg(next = Bool(false))
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val resp_valid = Reg(next = Vec.fill(io.requestor.size)(Bool(false)))
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val resp_ae = Reg(Bool())
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val r_req = Reg(new PTWReq)
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val r_req_dest = Reg(Bits())
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val r_pte = Reg(new PTE)
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val arb = Module(new RRArbiter(new PTWReq, n))
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arb.io.in <> io.requestor.map(_.req)
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arb.io.out.ready := state === s_ready
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val (pte, invalid_paddr) = {
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val tmp = new PTE().fromBits(io.mem.resp.bits.data)
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val res = Wire(init = new PTE().fromBits(io.mem.resp.bits.data))
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res.ppn := tmp.ppn(ppnBits-1, 0)
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when (tmp.r || tmp.w || tmp.x) {
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// for superpage mappings, make sure PPN LSBs are zero
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for (i <- 0 until pgLevels-1)
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when (count <= i && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0) { res.v := false }
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}
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(res, (tmp.ppn >> ppnBits) =/= 0)
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}
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val traverse = pte.table() && !invalid_paddr && count < pgLevels-1
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val pte_addr = if (!usingVM) 0.U else {
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val vpn_idxs = (0 until pgLevels).map(i => (r_req.addr >> (pgLevels-i-1)*pgLevelBits)(pgLevelBits-1,0))
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val vpn_idx = vpn_idxs(count)
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Cat(r_pte.ppn, vpn_idx) << log2Ceil(xLen/8)
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}
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when (arb.io.out.fire()) {
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r_req := arb.io.out.bits
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r_req_dest := arb.io.chosen
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r_pte.ppn := io.dpath.ptbr.ppn
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}
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val (pte_cache_hit, pte_cache_data) = {
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val size = 1 << log2Up(pgLevels * 2)
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val plru = new PseudoLRU(size)
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val valid = Reg(init = UInt(0, size))
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val tags = Reg(Vec(size, UInt(width = paddrBits)))
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val data = Reg(Vec(size, UInt(width = ppnBits)))
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val hits = tags.map(_ === pte_addr).asUInt & valid
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val hit = hits.orR
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when (io.mem.resp.valid && traverse && !hit) {
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val r = Mux(valid.andR, plru.replace, PriorityEncoder(~valid))
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valid := valid | UIntToOH(r)
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tags(r) := pte_addr
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data(r) := pte.ppn
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}
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when (hit && state === s_req) { plru.access(OHToUInt(hits)) }
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when (io.dpath.sfence.valid && !io.dpath.sfence.bits.rs1) { valid := 0 }
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for (i <- 0 until pgLevels-1)
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ccover(hit && state === s_req && count === i, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i")
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(hit && count < pgLevels-1, Mux1H(hits, data))
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}
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val l2_refill = RegNext(false.B)
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io.dpath.perf.l2miss := false
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val (l2_hit, l2_valid, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, Wire(new PTE), None) else {
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val code = new ParityCode
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require(isPow2(coreParams.nL2TLBEntries))
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val idxBits = log2Ceil(coreParams.nL2TLBEntries)
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val tagBits = vpnBits - idxBits
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class Entry extends Bundle {
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val tag = UInt(width = tagBits)
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val ppn = UInt(width = ppnBits)
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val d = Bool()
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val a = Bool()
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val u = Bool()
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val x = Bool()
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val w = Bool()
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val r = Bool()
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override def cloneType = new Entry().asInstanceOf[this.type]
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}
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val ram = SeqMem(coreParams.nL2TLBEntries, UInt(width = code.width(new Entry().getWidth)))
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val g = Reg(UInt(width = coreParams.nL2TLBEntries))
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val valid = RegInit(UInt(0, coreParams.nL2TLBEntries))
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val (r_tag, r_idx) = Split(r_req.addr, idxBits)
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when (l2_refill) {
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val entry = Wire(new Entry)
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entry := r_pte
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entry.tag := r_tag
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ram.write(r_idx, code.encode(entry.asUInt))
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val mask = UIntToOH(r_idx)
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valid := valid | mask
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g := Mux(r_pte.g, g | mask, g & ~mask)
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}
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when (io.dpath.sfence.valid) {
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valid :=
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Mux(io.dpath.sfence.bits.rs1, valid & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)),
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Mux(io.dpath.sfence.bits.rs2, valid & g, 0.U))
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}
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val s0_valid = !l2_refill && arb.io.out.fire()
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val s1_valid = RegNext(s0_valid)
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val s2_valid = RegNext(s1_valid)
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val s1_rdata = ram.read(arb.io.out.bits.addr(idxBits-1, 0), s0_valid)
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val s2_rdata = code.decode(RegEnable(s1_rdata, s1_valid))
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val s2_valid_bit = RegEnable(valid(r_idx), s1_valid)
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val s2_g = RegEnable(g(r_idx), s1_valid)
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when (s2_valid && s2_valid_bit && s2_rdata.error) { valid := 0.U }
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val s2_entry = s2_rdata.uncorrected.asTypeOf(new Entry)
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val s2_hit = s2_valid && s2_valid_bit && !s2_rdata.error && r_tag === s2_entry.tag
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io.dpath.perf.l2miss := s2_valid && !(s2_valid_bit && r_tag === s2_entry.tag)
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val s2_pte = Wire(new PTE)
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s2_pte := s2_entry
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s2_pte.g := s2_g
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s2_pte.v := true
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ccover(s2_hit, "L2_TLB_HIT", "L2 TLB hit")
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(s2_hit, s2_valid && s2_valid_bit, s2_pte, Some(ram))
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}
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io.mem.req.valid := state === s_req && !l2_valid
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io.mem.req.bits.phys := Bool(true)
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io.mem.req.bits.cmd := M_XRD
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io.mem.req.bits.typ := log2Ceil(xLen/8)
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io.mem.req.bits.addr := pte_addr
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io.mem.s1_kill := s1_kill || l2_hit
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io.mem.invalidate_lr := Bool(false)
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val pmaPgLevelHomogeneous = (0 until pgLevels) map { i =>
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TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits)))(pte_addr >> pgIdxBits << pgIdxBits).homogeneous
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}
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val pmaHomogeneous = pmaPgLevelHomogeneous(count)
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val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(pte_addr >> pgIdxBits << pgIdxBits, count)
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for (i <- 0 until io.requestor.size) {
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io.requestor(i).resp.valid := resp_valid(i)
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io.requestor(i).resp.bits.ae := resp_ae
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io.requestor(i).resp.bits.pte := r_pte
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io.requestor(i).resp.bits.level := count
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io.requestor(i).resp.bits.pte.ppn := pte_addr >> pgIdxBits
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io.requestor(i).resp.bits.homogeneous := pmpHomogeneous && pmaHomogeneous
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io.requestor(i).ptbr := io.dpath.ptbr
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io.requestor(i).status := io.dpath.status
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io.requestor(i).pmp := io.dpath.pmp
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}
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// control state machine
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switch (state) {
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is (s_ready) {
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when (arb.io.out.fire()) {
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state := s_req
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}
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count := UInt(0)
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}
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is (s_req) {
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when (pte_cache_hit) {
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s1_kill := true
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count := count + 1
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r_pte.ppn := pte_cache_data
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}.elsewhen (io.mem.req.fire()) {
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state := s_wait1
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}
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}
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is (s_wait1) {
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state := s_wait2
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}
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is (s_wait2) {
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when (io.mem.s2_nack) {
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state := s_req
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}
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when (io.mem.resp.valid) {
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r_pte := pte
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when (traverse) {
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state := s_req
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count := count + 1
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}.otherwise {
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l2_refill := pte.v && !invalid_paddr && count === pgLevels-1
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resp_ae := pte.v && invalid_paddr
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state := s_ready
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resp_valid(r_req_dest) := true
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}
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}
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when (io.mem.s2_xcpt.ae.ld) {
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resp_ae := true
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state := s_ready
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resp_valid(r_req_dest) := true
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}
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}
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}
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when (l2_hit) {
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state := s_ready
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resp_valid(r_req_dest) := true
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resp_ae := false
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r_pte := l2_pte
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count := pgLevels-1
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}
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for (i <- 0 until pgLevels) {
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val leaf = io.mem.resp.valid && !traverse && count === i
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ccover(leaf && pte.v && !invalid_paddr, s"L$i", s"successful page-table access, level $i")
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ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i")
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ccover(leaf && !io.mem.resp.bits.data(0), s"L${i}_INVALID_PTE", s"page not present, level $i")
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if (i != pgLevels-1)
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ccover(leaf && !pte.v && io.mem.resp.bits.data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i")
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}
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ccover(io.mem.resp.valid && count === pgLevels-1 && pte.table(), s"TOO_DEEP", s"page table too deep")
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ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access")
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ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table")
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def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
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if (usingVM) cover(cond, s"PTW_$label", "MemorySystem;;" + desc)
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}
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/** Mix-ins for constructing tiles that might have a PTW */
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trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile =>
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val module: CanHavePTWModule
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var nPTWPorts = 1
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nDCachePorts += usingPTW.toInt
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}
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trait CanHavePTWModule extends HasHellaCacheModule {
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val outer: CanHavePTW
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val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
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val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p))
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if (outer.usingPTW)
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dcachePorts += ptw.io.mem
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}
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