364 lines
16 KiB
Scala
364 lines
16 KiB
Scala
package uncore
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import Chisel._
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import Constants._
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class TrackerProbeData(implicit conf: UncoreConfiguration) extends Bundle {
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val client_id = Bits(width = conf.ln.idBits)
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}
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class TrackerAllocReq(implicit conf: UncoreConfiguration) extends Bundle {
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val acquire = new Acquire()
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val client_id = Bits(width = conf.ln.idBits)
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override def clone = { new TrackerAllocReq().asInstanceOf[this.type] }
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}
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class TrackerDependency extends Bundle {
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val master_xact_id = Bits(width = MASTER_XACT_ID_MAX_BITS)
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}
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case class UncoreConfiguration(co: CoherencePolicyWithUncached, ln: LogicalNetworkConfiguration)
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abstract class CoherenceAgent(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent {
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val io = new Bundle {
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val client = (new TileLinkIO).flip
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val master = new UncachedTileLinkIO
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val incoherent = Vec(conf.nClients) { Bool() }.asInput
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}
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}
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class L2CoherenceAgent(bankId: Int)(implicit conf: UncoreConfiguration) extends CoherenceAgent()(conf.ln)
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{
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implicit val lnConf = conf.ln
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val co = conf.co
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val trackerList = new WritebackTracker(0, bankId) +: (1 to NGLOBAL_XACTS).map(new AcquireTracker(_, bankId))
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val release_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth must >= NPRIMARY
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val acquire_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth should >= NPRIMARY
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trackerList.map(_.io.tile_incoherent := io.incoherent.toBits)
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// Handle acquire transaction initiation
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val acquire = io.client.acquire
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val acquire_data = io.client.acquire_data
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val acq_dep_deq = acquire_data_dep_q.io.deq
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val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
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val block_acquires = any_acquire_conflict || (!acquire_data_dep_q.io.enq.ready && co.messageHasData(acquire.bits.payload))
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val alloc_arb = (new Arbiter(trackerList.size)) { Bool() }
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.client
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alloc_arb.io.in(i).valid := t.acquire.ready
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t.acquire.bits := acquire.bits
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t.acquire.valid := alloc_arb.io.in(i).ready
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t.acquire_data.bits := acquire_data.bits
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t.acquire_data.valid := acquire_data.valid
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trackerList(i).io.acquire_data_dep.bits := acq_dep_deq.bits
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trackerList(i).io.acquire_data_dep.valid := acq_dep_deq.valid
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}
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acquire.ready := trackerList.map(_.io.client.acquire.ready).reduce(_||_) && !block_acquires
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acquire_data.ready := trackerList.map(_.io.client.acquire_data.ready).reduce(_||_)
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acquire_data_dep_q.io.enq.valid := acquire.valid && acquire.ready && co.messageHasData(acquire.bits.payload)
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acquire_data_dep_q.io.enq.bits.master_xact_id := OHToUFix(alloc_arb.io.in.map(_.ready))
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acq_dep_deq.ready := trackerList.map(_.io.acquire_data_dep.ready).reduce(_||_)
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alloc_arb.io.out.ready := acquire.valid && !block_acquires
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// Handle probe request generation
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val probe_arb = (new Arbiter(trackerList.size)){(new LogicalNetworkIO){ new Probe }}
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io.client.probe <> probe_arb.io.out
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probe_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.client.probe }
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// Handle probe replies, which may or may not have data
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val release = io.client.release
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val release_data = io.client.release_data
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val voluntary = co.isVoluntary(release.bits.payload)
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val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_)
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val block_releases = (!release_data_dep_q.io.enq.ready && co.messageHasData(release.bits.payload))
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val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)){Bool()}.lastIndexWhere{b: Bool => b}
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val idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UFix(0)), release.bits.payload.master_xact_id)
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.client
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t.release.bits := release.bits
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t.release.valid := release.valid && (idx === UFix(i)) && !block_releases
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t.release_data.bits := release_data.bits
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t.release_data.valid := release_data.valid
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trackerList(i).io.release_data_dep.bits := release_data_dep_q.io.deq.bits
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trackerList(i).io.release_data_dep.valid := release_data_dep_q.io.deq.valid
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}
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release.ready := Vec(trackerList.map(_.io.client.release.ready)){Bool()}(idx) && !block_releases
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release_data.ready := trackerList.map(_.io.client.release_data.ready).reduce(_||_)
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release_data_dep_q.io.enq.valid := release.valid && release.ready && co.messageHasData(release.bits.payload)
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release_data_dep_q.io.enq.bits.master_xact_id := idx
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release_data_dep_q.io.deq.ready := trackerList.map(_.io.release_data_dep.ready).reduce(_||_)
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// Reply to initial requestor
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val grant_arb = (new Arbiter(trackerList.size)){(new LogicalNetworkIO){ new Grant }}
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io.client.grant <> grant_arb.io.out
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grant_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.client.grant }
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// Free finished transactions
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val ack = io.client.grant_ack
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trackerList.map(_.io.client.grant_ack.valid := ack.valid)
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trackerList.map(_.io.client.grant_ack.bits := ack.bits)
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ack.ready := Bool(true)
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// Create an arbiter for the one memory port
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val outer_arb = new UncachedTileLinkIOArbiter(trackerList.size)
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outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.master }
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io.master <> outer_arb.io.out
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}
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abstract class XactTracker()(implicit conf: UncoreConfiguration) extends Component with OuterRequestGenerator {
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val co = conf.co
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implicit val ln = conf.ln
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val io = new Bundle {
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val client = (new TileLinkIO).flip
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val master = new UncachedTileLinkIO
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val tile_incoherent = Bits(INPUT, conf.ln.nClients)
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val release_data_dep = (new FIFOIO) { new TrackerDependency }.flip
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val acquire_data_dep = (new FIFOIO) { new TrackerDependency }.flip
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val has_acquire_conflict = Bool(OUTPUT)
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val has_release_conflict = Bool(OUTPUT)
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}
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}
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class WritebackTracker(trackerId: Int, bankId: Int)(implicit conf: UncoreConfiguration) extends XactTracker()(conf) {
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val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(4){ UFix() }
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val state = Reg(resetVal = s_idle)
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val xact = Reg{ new Release }
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val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients)))
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val release_data_needs_write = Reg(resetVal = Bool(false))
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val mem_cmd_sent = Reg(resetVal = Bool(false))
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val cmd_to_write = co.getUncachedWriteAcquire(xact.addr, UFix(trackerId))
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val cmd_to_read = co.getUncachedReadAcquire(xact.addr, UFix(trackerId))
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io.acquire_data_dep.ready := Bool(false)
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io.release_data_dep.ready := Bool(false)
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io.has_acquire_conflict := Bool(false)
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io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.client.release.bits.payload.addr) && (state != s_idle)
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io.master.grant.ready := Bool(false)
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io.master.acquire.valid := Bool(false)
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io.master.acquire.bits.payload := cmd_to_write
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//TODO io.master.acquire.bits.header.dst
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io.master.acquire.bits.header.src := UFix(bankId)
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io.master.acquire_data.valid := Bool(false)
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io.master.acquire_data.bits.payload.data := UFix(0)
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//TODO io.master.acquire_data.bits.header.dst
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io.master.acquire_data.bits.header.src := UFix(bankId)
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io.client.acquire.ready := Bool(false)
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io.client.acquire_data.ready := Bool(false)
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io.client.probe.valid := Bool(false)
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io.client.release.ready := Bool(false)
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io.client.release_data.ready := Bool(false) // DNC
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io.client.grant.valid := Bool(false)
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io.client.grant.bits.payload.g_type := co.getGrantType(xact, UFix(0))
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io.client.grant.bits.payload.client_xact_id := xact.client_xact_id
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io.client.grant.bits.payload.master_xact_id := UFix(trackerId)
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io.client.grant.bits.header.dst := init_client_id_
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io.client.grant.bits.header.src := UFix(bankId)
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io.client.grant_ack.valid := Bool(false)
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switch (state) {
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is(s_idle) {
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io.client.release.ready := Bool(true)
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when( io.client.release.valid ) {
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xact := io.client.release.bits.payload
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init_client_id_ := io.client.release.bits.header.src
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release_data_needs_write := co.messageHasData(io.client.release.bits.payload)
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mem_cnt := UFix(0)
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mem_cmd_sent := Bool(false)
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state := s_mem
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}
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}
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is(s_mem) {
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when (release_data_needs_write) {
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doOuterReqWrite(io.master.acquire,
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io.master.acquire_data,
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io.client.release_data,
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release_data_needs_write,
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mem_cmd_sent,
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io.release_data_dep.ready,
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io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(trackerId)))
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} . otherwise { state := s_ack }
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}
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is(s_ack) {
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io.client.grant.valid := Bool(true)
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when(io.client.grant.ready) { state := s_idle }
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}
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}
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}
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class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: UncoreConfiguration) extends XactTracker()(conf) {
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val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() }
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val state = Reg(resetVal = s_idle)
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val xact = Reg{ new Acquire }
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val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients)))
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//TODO: Will need id reg for merged release xacts
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val init_sharer_cnt_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients)))
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val grant_type = co.getGrantType(xact.a_type, init_sharer_cnt_)
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val release_count = if (conf.ln.nClients == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients)))
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val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nClients))
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val curr_p_id = PriorityEncoder(probe_flags)
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val x_needs_read = Reg(resetVal = Bool(false))
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val acquire_data_needs_write = Reg(resetVal = Bool(false))
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val release_data_needs_write = Reg(resetVal = Bool(false))
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val cmd_to_write = co.getUncachedWriteAcquire(xact.addr, UFix(trackerId))
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val cmd_to_read = co.getUncachedReadAcquire(xact.addr, UFix(trackerId))
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val a_w_mem_cmd_sent = Reg(resetVal = Bool(false))
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val r_w_mem_cmd_sent = Reg(resetVal = Bool(false))
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val probe_initial_flags = Bits(width = conf.ln.nClients)
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probe_initial_flags := Bits(0)
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if (conf.ln.nClients > 1) {
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// issue self-probes for uncached read xacts to facilitate I$ coherence
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val probe_self = Bool(true) //co.needsSelfProbe(io.client.acquire.bits.payload)
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val myflag = Mux(probe_self, Bits(0), UFixToOH(io.client.acquire.bits.header.src(log2Up(conf.ln.nClients)-1,0)))
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probe_initial_flags := ~(io.tile_incoherent | myflag)
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}
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io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, io.client.acquire.bits.payload.addr) && (state != s_idle)
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io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.client.release.bits.payload.addr) && (state != s_idle)
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io.master.acquire.valid := Bool(false)
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io.master.acquire.bits.payload := co.getUncachedReadAcquire(xact.addr, UFix(trackerId))
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//TODO io.master.acquire.bits.header.dst
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io.master.acquire.bits.header.src := UFix(bankId)
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io.master.acquire_data.valid := Bool(false)
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io.master.acquire_data.bits.payload.data := UFix(0)
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//TODO io.master.acquire_data.bits.header.dst
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io.master.acquire_data.bits.header := UFix(bankId)
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io.client.probe.valid := Bool(false)
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io.client.probe.bits.payload.p_type := co.getProbeType(xact.a_type, UFix(0))
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io.client.probe.bits.payload.master_xact_id := UFix(trackerId)
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io.client.probe.bits.payload.addr := xact.addr
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io.client.probe.bits.header.dst := UFix(0)
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io.client.probe.bits.header.src := UFix(bankId)
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io.client.grant.bits.payload.data := io.master.grant.bits.payload.data
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io.client.grant.bits.payload.g_type := grant_type
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io.client.grant.bits.payload.client_xact_id := xact.client_xact_id
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io.client.grant.bits.payload.master_xact_id := UFix(trackerId)
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io.client.grant.bits.header.dst := init_client_id_
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io.client.grant.bits.header.src := UFix(bankId)
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io.client.grant.valid := (io.master.grant.valid && (UFix(trackerId) === io.master.grant.bits.payload.client_xact_id))
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io.client.acquire.ready := Bool(false)
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io.client.acquire_data.ready := Bool(false)
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io.acquire_data_dep.ready := Bool(false)
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io.client.release.ready := Bool(false)
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io.client.release_data.ready := Bool(false)
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io.release_data_dep.ready := Bool(false)
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io.master.grant.ready := io.client.grant.ready
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io.client.grant_ack.valid := Bool(false)
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switch (state) {
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is(s_idle) {
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io.client.acquire.ready := Bool(true)
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when( io.client.acquire.valid ) {
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xact := io.client.acquire.bits.payload
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init_client_id_ := io.client.acquire.bits.header.src
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init_sharer_cnt_ := UFix(conf.ln.nClients) // TODO: Broadcast only
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acquire_data_needs_write := co.messageHasData(io.client.acquire.bits.payload)
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x_needs_read := co.needsOuterRead(io.client.acquire.bits.payload.a_type, UFix(0))
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probe_flags := probe_initial_flags
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mem_cnt := UFix(0)
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r_w_mem_cmd_sent := Bool(false)
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a_w_mem_cmd_sent := Bool(false)
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if(conf.ln.nClients > 1) {
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release_count := PopCount(probe_initial_flags)
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state := Mux(probe_initial_flags.orR, s_probe, s_mem)
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} else state := s_mem
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}
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}
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is(s_probe) {
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when(probe_flags.orR) {
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io.client.probe.valid := Bool(true)
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io.client.probe.bits.header.dst := curr_p_id
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}
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when(io.client.probe.ready) {
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probe_flags := probe_flags & ~(UFixToOH(curr_p_id))
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}
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io.client.release.ready := Bool(true)
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when(io.client.release.valid) {
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if(conf.ln.nClients > 1) release_count := release_count - UFix(1)
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when(release_count === UFix(1)) {
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state := s_mem
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}
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release_data_needs_write := release_data_needs_write || co.messageHasData(io.client.release.bits.payload)
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}
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}
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is(s_mem) {
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when (release_data_needs_write) {
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doOuterReqWrite(io.master.acquire,
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io.master.acquire_data,
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io.client.release_data,
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release_data_needs_write,
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r_w_mem_cmd_sent,
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io.release_data_dep.ready,
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io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(trackerId)))
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} . elsewhen(acquire_data_needs_write) {
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doOuterReqWrite(io.master.acquire,
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io.master.acquire_data,
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io.client.acquire_data,
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acquire_data_needs_write,
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a_w_mem_cmd_sent,
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io.acquire_data_dep.ready,
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io.acquire_data_dep.valid && (io.acquire_data_dep.bits.master_xact_id === UFix(trackerId)))
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} . elsewhen (x_needs_read) {
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doOuterReqRead(io.master.acquire, x_needs_read)
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} . otherwise {
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state := Mux(co.needsAckReply(xact.a_type, UFix(0)), s_ack,
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Mux(co.requiresAck(io.client.grant.bits.payload), s_busy, s_idle))
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}
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}
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is(s_ack) {
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io.client.grant.valid := Bool(true)
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when(io.client.grant.ready) { state := Mux(co.requiresAck(io.client.grant.bits.payload), s_busy, s_idle) }
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}
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is(s_busy) { // Nothing left to do but wait for transaction to complete
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when (io.client.grant_ack.valid && io.client.grant_ack.bits.payload.master_xact_id === UFix(trackerId)) {
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state := s_idle
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}
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}
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}
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}
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abstract trait OuterRequestGenerator {
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val cmd_to_write: Acquire
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val cmd_to_read: Acquire
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val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
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val mem_cnt_next = mem_cnt + UFix(1)
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def doOuterReqWrite[T <: Data](master_acq: FIFOIO[LogicalNetworkIO[Acquire]], master_acq_data: FIFOIO[LogicalNetworkIO[AcquireData]], client_data: FIFOIO[LogicalNetworkIO[T]], trigger: Bool, cmd_sent: Bool, pop_dep: Bool, at_front_of_dep_queue: Bool) {
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master_acq.bits.payload := cmd_to_write
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master_acq_data.bits.payload := client_data.bits.payload
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when(master_acq.ready && master_acq.valid) {
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cmd_sent := Bool(true)
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}
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when (at_front_of_dep_queue) {
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master_acq.valid := !cmd_sent && master_acq_data.ready && client_data.valid
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when (master_acq.ready || cmd_sent) {
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master_acq_data.valid := client_data.valid
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when(master_acq_data.ready) {
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client_data.ready:= Bool(true)
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when (client_data.valid) {
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mem_cnt := mem_cnt_next
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when(mem_cnt === UFix(REFILL_CYCLES-1)) {
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pop_dep := Bool(true)
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trigger := Bool(false)
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}
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}
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}
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}
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}
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}
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def doOuterReqRead(master_acq: FIFOIO[LogicalNetworkIO[Acquire]], trigger: Bool) {
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master_acq.valid := Bool(true)
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master_acq.bits.payload := cmd_to_read
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when(master_acq.ready) {
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trigger := Bool(false)
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}
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}
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}
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