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ALU.scala
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Don't route branch comparison result through ALU output mux
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2017-10-07 17:36:24 -07:00 |
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AMOALU.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Breakpoint.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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BTB.scala
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Fix BTB not being refilled on some indirect jumps
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2017-07-26 02:13:43 -07:00 |
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BusErrorUnit.scala
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IntNodes: moved from tilelink to their own package
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2017-10-25 16:56:51 -07:00 |
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Consts.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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CSR.scala
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csr: allow for superscalar decode (#1069)
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2017-10-25 13:58:26 -07:00 |
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DCache.scala
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Merge pull request #1039 from freechipsproject/tile-crossing-params
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2017-10-11 17:12:03 -07:00 |
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Decode.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Events.scala
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Add method to print perf events
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2017-07-25 15:19:16 -07:00 |
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Frontend.scala
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Define fetchBytes in HasCoreParams, not Frontend
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2017-10-03 17:34:18 -07:00 |
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HellaCache.scala
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coreplex: first cut at using RocketCrossingParams
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2017-10-10 12:02:04 -07:00 |
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HellaCacheArbiter.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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IBuf.scala
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Add instruction-trace port
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2017-09-19 22:59:57 -07:00 |
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ICache.scala
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Fix ITIM bug overwriting I$ contents when deallocating ITIM (#1079)
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2017-10-31 00:49:56 -07:00 |
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IDecode.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Instructions.scala
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Add RVC instruction patterns
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2017-07-25 15:19:16 -07:00 |
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Multiplier.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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NBDcache.scala
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tilelink: split Acquire into Acquire{Block,Perm} (#1030)
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2017-10-05 12:49:49 -07:00 |
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package.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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PMP.scala
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Move microarchitecture-neutral params from Rocket to Core
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2017-10-03 17:34:18 -07:00 |
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PTW.scala
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Conditionalize some covers that are sometimes impossible (#1043)
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2017-10-10 17:14:33 -07:00 |
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RocketCore.scala
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csr: allow for superscalar decode (#1069)
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2017-10-25 13:58:26 -07:00 |
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RVC.scala
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Expand C.UNIMP correctly (#1052)
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2017-10-12 14:00:14 -07:00 |
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ScratchpadSlavePort.scala
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diplomacy: use new node style chaining
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2017-10-28 11:34:16 -07:00 |
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SimpleHellaCacheIF.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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TLB.scala
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Merge pull request #1039 from freechipsproject/tile-crossing-params
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2017-10-11 17:12:03 -07:00 |
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TLBPermissions.scala
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rocket: only cache when AcquireT is possible
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2017-10-10 18:06:58 -07:00 |
3db066303b