142 lines
4.4 KiB
Scala
142 lines
4.4 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.devices.debug
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import Chisel._
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import chisel3.core.{IntParam, Input, Output}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.jtag._
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import freechips.rocketchip.util._
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/** A knob selecting one of the two possible debug interfaces */
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case object IncludeJtagDTM extends Field[Boolean](false)
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/** A wrapper bundle containing one of the two possible debug interfaces */
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class DebugIO(implicit val p: Parameters) extends ParameterizedBundle()(p) with CanHavePSDTestModeIO {
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val clockeddmi = (!p(IncludeJtagDTM)).option(new ClockedDMIIO().flip)
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val systemjtag = (p(IncludeJtagDTM)).option(new SystemJTAGIO)
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val ndreset = Bool(OUTPUT)
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val dmactive = Bool(OUTPUT)
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}
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/** Either adds a JTAG DTM to system, and exports a JTAG interface,
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* or exports the Debug Module Interface (DMI), based on a global parameter.
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*/
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trait HasPeripheryDebug { this: BaseSubsystem =>
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val debug = LazyModule(new TLDebugModule(pbus.beatBytes))
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pbus.toVariableWidthSlave(Some("debug")){ debug.node }
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}
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trait HasPeripheryDebugBundle {
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implicit val p: Parameters
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val debug: DebugIO
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def connectDebug(c: Clock,
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r: Bool,
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out: Bool,
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tckHalfPeriod: Int = 2,
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cmdDelay: Int = 2,
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psd: PSDTestMode = new PSDTestMode().fromBits(0.U)): Unit = {
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debug.clockeddmi.foreach { d =>
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val dtm = Module(new SimDTM).connect(c, r, d, out)
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}
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debug.systemjtag.foreach { sj =>
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val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, c, r, ~r, out)
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sj.reset := r
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sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
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}
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debug.psd.foreach { _ <> psd }
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}
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}
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trait HasPeripheryDebugModuleImp extends LazyModuleImp with HasPeripheryDebugBundle {
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val outer: HasPeripheryDebug
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val debug = IO(new DebugIO)
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debug.clockeddmi.foreach { dbg => outer.debug.module.io.dmi <> dbg }
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val dtm = debug.systemjtag.map { sj =>
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val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleParams).nDMIAddrSize, p(JtagDTMKey)))
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dtm.io.jtag <> sj.jtag
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dtm.clock := sj.jtag.TCK
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dtm.io.jtag_reset := sj.reset
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dtm.io.jtag_mfr_id := sj.mfr_id
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dtm.reset := dtm.io.fsmReset
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outer.debug.module.io.dmi.dmi <> dtm.io.dmi
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outer.debug.module.io.dmi.dmiClock := sj.jtag.TCK
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val psd = debug.psd.getOrElse(Wire(new PSDTestMode).fromBits(0.U))
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outer.debug.module.io.psd <> psd
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outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch", psd)
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dtm
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}
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debug.ndreset := outer.debug.module.io.ctrl.ndreset
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debug.dmactive := outer.debug.module.io.ctrl.dmactive
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// TODO in inheriting traits: Set this to something meaningful, e.g. "component is in reset or powered down"
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outer.debug.module.io.ctrl.debugUnavail.foreach { _ := Bool(false) }
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}
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class SimDTM(implicit p: Parameters) extends BlackBox {
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val io = new Bundle {
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val clk = Clock(INPUT)
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val reset = Bool(INPUT)
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val debug = new DMIIO
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val exit = UInt(OUTPUT, 32)
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}
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def connect(tbclk: Clock, tbreset: Bool, dutio: ClockedDMIIO, tbsuccess: Bool) = {
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io.clk := tbclk
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io.reset := tbreset
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dutio.dmi <> io.debug
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dutio.dmiClock := tbclk
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dutio.dmiReset := tbreset
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tbsuccess := io.exit === UInt(1)
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when (io.exit >= UInt(2)) {
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printf("*** FAILED *** (exit code = %d)\n", io.exit >> UInt(1))
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stop(1)
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}
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}
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}
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class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam(tickDelay))) {
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val io = new Bundle {
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val clock = Clock(INPUT)
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val reset = Bool(INPUT)
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val jtag = new JTAGIO(hasTRSTn = true)
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val enable = Bool(INPUT)
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val init_done = Bool(INPUT)
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val exit = UInt(OUTPUT, 32)
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}
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def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, init_done: Bool, tbsuccess: Bool) = {
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dutio <> io.jtag
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io.clock := tbclock
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io.reset := tbreset
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io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.")
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io.init_done := init_done
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// Success is determined by the gdbserver
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// which is controlling this simulation.
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tbsuccess := io.exit === UInt(1)
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when (io.exit >= UInt(2)) {
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printf("*** FAILED *** (exit code = %d)\n", io.exit >> UInt(1))
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stop(1)
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}
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}
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}
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