279 lines
13 KiB
Scala
279 lines
13 KiB
Scala
package rocket
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import Chisel._
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import Node._
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import Constants._
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import Instructions._
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import hwacha.Constants._
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class ioCtrlDpathVec extends Bundle
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{
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val inst = Bits(INPUT, 32)
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val appvl0 = Bool(INPUT)
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val pfq = Bool(INPUT)
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val wen = Bool(OUTPUT)
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val fn = Bits(OUTPUT, 2)
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val sel_vcmd = Bits(OUTPUT, 3)
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val sel_vimm = Bits(OUTPUT, 1)
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val sel_vimm2 = Bits(OUTPUT, 1)
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}
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class ioCtrlVecInterface extends Bundle
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{
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val vcmdq = new FIFOIO()(Bits(width = SZ_VCMD))
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val vximm1q = new FIFOIO()(Bits(width = SZ_VIMM))
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val vximm2q = new FIFOIO()(Bits(width = SZ_VSTRIDE))
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val vcntq = new FIFOIO()(Bits(width = SZ_VLEN+1))
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val vpfcmdq = new FIFOIO()(Bits(width = SZ_VCMD))
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val vpfximm1q = new FIFOIO()(Bits(width = SZ_VIMM))
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val vpfximm2q = new FIFOIO()(Bits(width = SZ_VSTRIDE))
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val vpfcntq = new FIFOIO()(Bits(width = SZ_VLEN))
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val vcmdq_user_ready = Bool(INPUT)
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val vximm1q_user_ready = Bool(INPUT)
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val vximm2q_user_ready = Bool(INPUT)
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val vfence_ready = Bool(INPUT)
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val irq = Bool(INPUT)
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val irq_cause = UFix(INPUT, 5)
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val exception = Bool(OUTPUT)
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val evac = Bool(OUTPUT)
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val kill = Bool(OUTPUT)
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val hold = Bool(OUTPUT)
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}
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class ioCtrlVec extends Bundle
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{
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val dpath = new ioCtrlDpathVec()
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val iface = new ioCtrlVecInterface()
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val valid = Bool(INPUT)
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val s = Bool(INPUT)
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val sr_ev = Bool(INPUT)
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val exception = Bool(INPUT)
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val eret = Bool(INPUT)
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val replay = Bool(OUTPUT)
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val vfence_ready = Bool(OUTPUT)
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val irq = Bool(OUTPUT)
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val irq_cause = UFix(OUTPUT, 5)
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}
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class rocketCtrlVecSigs extends Bundle
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{
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val valid = Bool()
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val sel_vcmd = Bits(width = 3)
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val sel_vimm = Bits(width = 1)
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val sel_vimm2 = Bits(width = 1)
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val wen = Bool()
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val fn = Bits(width = 2)
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val appvlmask = Bool()
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val enq_cmdq = Bool()
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val enq_ximm1q = Bool()
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val enq_ximm2q = Bool()
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val enq_cntq = Bool()
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val enq_pfcmdq = Bool()
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val enq_pfximm1q = Bool()
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val enq_pfximm2q = Bool()
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val enq_pfcntq = Bool()
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val pfaq = Bool()
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val vfence = Bool()
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val xcptevac = Bool()
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val xcptkill = Bool()
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val xcpthold = Bool()
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}
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class rocketCtrlVecDecoder extends Component
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{
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val io = new Bundle
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{
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val inst = Bits(INPUT, 32)
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val sigs = new rocketCtrlVecSigs().asOutput
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}
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val veccs =
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ListLookup(io.inst,
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// appvlmask
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// | vcmdq
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// | | vximm1q
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// | | | vximm2q
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// | | | | vcntq
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// | | | | | vpfcmdq
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// | | | | | | vpfximm1q
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// | | | | | | | vpfximm2q
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// | | | | | | | | vpfcntq
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// | | | | | | | | | pfq
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// | | | | | | | | | | vfence
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// | | | | | | | | | | | xcptevac
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// | | | | | | | | | | | | xcptkill
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// wen | | | | | | | | | | | | | xcpthold
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// val vcmd vimm vimm2 | fn | | | | | | | | | | | | | |
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// | | | | | | | | | | | | | | | | | | | |
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List(N,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,N,N),Array(
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VVCFGIVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_CFGVL,N,Y,Y,N,N,Y,Y,N,N,N,Y,N,N,N),
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VVCFG-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, N,VEC_CFG, N,Y,Y,N,N,Y,Y,N,N,N,Y,N,N,N),
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VSETVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_VL, N,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
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VF-> List(Y,VCMD_I, VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N,N,N),
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VMVV-> List(Y,VCMD_TX,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N,N,N),
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VMSV-> List(Y,VCMD_TX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N,N,N),
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VFMVV-> List(Y,VCMD_TF,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N,N,N),
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FENCE_V_L-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N,N,N),
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FENCE_V_G-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N,N,N),
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VLD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
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VLW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
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VLWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
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VLH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
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VLHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
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VLB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
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VLBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
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VSD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
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VSW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
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VSH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
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VSB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
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VFLD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
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VFLW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
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VFSD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
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VFSW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N,N,N),
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VLSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
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VLSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
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VLSTWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
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VLSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
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VLSTHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
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VLSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
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VLSTBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
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VSSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
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VSSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
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VSSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
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VSSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
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VFLSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
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VFLSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
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VFSSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
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VFSSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N,N,N),
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VENQCMD-> List(Y,VCMD_A, VIMM_X, VIMM2_X, N,VEC_FN_N, N,Y,N,N,N,Y,N,N,N,Y,N,N,N,N),
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VENQIMM1-> List(Y,VCMD_X, VIMM_ALU, VIMM2_X, N,VEC_FN_N, N,N,Y,N,N,N,Y,N,N,Y,N,N,N,N),
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VENQIMM2-> List(Y,VCMD_X, VIMM_X, VIMM2_ALU,N,VEC_FN_N, N,N,N,Y,N,N,N,Y,N,Y,N,N,N,N),
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VENQCNT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,Y,N,N,N,Y,Y,N,N,N,N),
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VXCPTEVAC-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,Y,N,N),
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VXCPTKILL-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,Y,N),
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VXCPTHOLD-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,N,N,Y)
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))
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val valid :: sel_vcmd :: sel_vimm :: sel_vimm2 :: wen :: fn :: appvlmask :: veccs0 = veccs
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val enq_cmdq :: enq_ximm1q :: enq_ximm2q :: enq_cntq :: veccs1 = veccs0
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val enq_pfcmdq :: enq_pfximm1q :: enq_pfximm2q :: enq_pfcntq :: veccs2 = veccs1
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val pfaq :: vfence :: xcptevac :: xcptkill :: xcpthold :: Nil = veccs2
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io.sigs.valid := valid.toBool
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io.sigs.sel_vcmd := sel_vcmd
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io.sigs.sel_vimm := sel_vimm
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io.sigs.sel_vimm2 := sel_vimm2
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io.sigs.wen := wen.toBool
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io.sigs.fn := fn
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io.sigs.appvlmask := appvlmask.toBool
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io.sigs.enq_cmdq := enq_cmdq.toBool
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io.sigs.enq_ximm1q := enq_ximm1q.toBool
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io.sigs.enq_ximm2q := enq_ximm2q.toBool
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io.sigs.enq_cntq := enq_cntq.toBool
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io.sigs.enq_pfcmdq := enq_pfcmdq.toBool
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io.sigs.enq_pfximm1q := enq_pfximm1q.toBool
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io.sigs.enq_pfximm2q := enq_pfximm2q.toBool
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io.sigs.enq_pfcntq := enq_pfcntq.toBool
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io.sigs.pfaq := pfaq.toBool
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io.sigs.vfence := vfence.toBool
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io.sigs.xcptevac := xcptevac.toBool
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io.sigs.xcptkill := xcptkill.toBool
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io.sigs.xcpthold := xcpthold.toBool
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}
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class rocketCtrlVec extends Component
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{
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val io = new ioCtrlVec()
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val dec = new rocketCtrlVecDecoder()
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dec.io.inst := io.dpath.inst
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val valid_common = io.valid && io.sr_ev && dec.io.sigs.valid && !(dec.io.sigs.appvlmask && io.dpath.appvl0)
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val enq_pfcmdq_mask_pfq = dec.io.sigs.enq_pfcmdq && (!dec.io.sigs.pfaq || io.dpath.pfq)
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val enq_pfximm1q_mask_pfq = dec.io.sigs.enq_pfximm1q && (!dec.io.sigs.pfaq || io.dpath.pfq)
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val enq_pfximm2q_mask_pfq = dec.io.sigs.enq_pfximm2q && (!dec.io.sigs.pfaq || io.dpath.pfq)
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val enq_pfcntq_mask_pfq = dec.io.sigs.enq_pfcntq && (!dec.io.sigs.pfaq || io.dpath.pfq)
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val mask_cmdq_ready = !dec.io.sigs.enq_cmdq || io.s && io.iface.vcmdq.ready || !io.s && io.iface.vcmdq_user_ready
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val mask_ximm1q_ready = !dec.io.sigs.enq_ximm1q || io.s && io.iface.vximm1q.ready || !io.s && io.iface.vximm1q_user_ready
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val mask_ximm2q_ready = !dec.io.sigs.enq_ximm2q || io.s && io.iface.vximm2q.ready || !io.s && io.iface.vximm2q_user_ready
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val mask_cntq_ready = !dec.io.sigs.enq_cntq || io.iface.vcntq.ready
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val mask_pfcmdq_ready = !enq_pfcmdq_mask_pfq || io.iface.vpfcmdq.ready
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val mask_pfximm1q_ready = !enq_pfximm1q_mask_pfq || io.iface.vpfximm1q.ready
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val mask_pfximm2q_ready = !enq_pfximm2q_mask_pfq || io.iface.vpfximm2q.ready
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val mask_pfcntq_ready = !enq_pfcntq_mask_pfq || io.iface.vpfcntq.ready
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io.dpath.wen := dec.io.sigs.wen
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io.dpath.fn := dec.io.sigs.fn
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io.dpath.sel_vcmd := dec.io.sigs.sel_vcmd
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io.dpath.sel_vimm := dec.io.sigs.sel_vimm
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io.dpath.sel_vimm2 := dec.io.sigs.sel_vimm2
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io.iface.vcmdq.valid :=
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valid_common &&
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dec.io.sigs.enq_cmdq && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
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mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
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io.iface.vximm1q.valid :=
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valid_common &&
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mask_cmdq_ready && dec.io.sigs.enq_ximm1q && mask_ximm2q_ready && mask_cntq_ready &&
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mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
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io.iface.vximm2q.valid :=
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valid_common &&
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mask_cmdq_ready && mask_ximm1q_ready && dec.io.sigs.enq_ximm2q && mask_cntq_ready &&
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mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
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io.iface.vcntq.valid :=
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valid_common &&
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mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && dec.io.sigs.enq_cntq &&
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mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
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io.iface.vpfcmdq.valid :=
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valid_common &&
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mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
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enq_pfcmdq_mask_pfq && mask_pfximm1q_ready && mask_pfximm2q_ready && mask_pfcntq_ready
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io.iface.vpfximm1q.valid :=
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valid_common &&
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mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
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mask_pfcmdq_ready && enq_pfximm1q_mask_pfq && mask_pfximm2q_ready && mask_pfcntq_ready
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io.iface.vpfximm2q.valid :=
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valid_common &&
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mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
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mask_pfcmdq_ready && mask_pfximm1q_ready && enq_pfximm2q_mask_pfq && mask_pfcntq_ready
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io.iface.vpfcntq.valid :=
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valid_common &&
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mask_cmdq_ready && mask_ximm1q_ready && mask_ximm2q_ready && mask_cntq_ready &&
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mask_pfcmdq_ready && mask_pfximm1q_ready && mask_pfximm2q_ready && enq_pfcntq_mask_pfq
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io.replay := valid_common && (
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!mask_cmdq_ready || !mask_ximm1q_ready || !mask_ximm2q_ready || !mask_cntq_ready ||
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!mask_pfcmdq_ready || !mask_pfximm1q_ready || !mask_pfximm2q_ready || !mask_pfcntq_ready ||
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dec.io.sigs.vfence && !io.iface.vfence_ready
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)
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io.iface.exception := io.exception && io.sr_ev
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val reg_hold = Reg(resetVal = Bool(false))
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when (valid_common && dec.io.sigs.xcpthold) { reg_hold := Bool(true) }
|
|
when (io.eret) { reg_hold := Bool(false) }
|
|
|
|
io.iface.evac := valid_common && dec.io.sigs.xcptevac
|
|
io.iface.kill := valid_common && dec.io.sigs.xcptkill
|
|
io.iface.hold := reg_hold
|
|
|
|
io.vfence_ready := !io.sr_ev || io.iface.vfence_ready
|
|
io.irq := io.iface.irq
|
|
io.irq_cause := io.iface.irq_cause
|
|
}
|