69 lines
2.0 KiB
Plaintext
69 lines
2.0 KiB
Plaintext
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#--------------------------------------------------------------------
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# Sources
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#--------------------------------------------------------------------
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# Verilog sources
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sim_vsrcs = \
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$(generated_dir)/$(FPGAMODEL).v \
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$(generated_dir)/$(FPGAMODEL)Mem.v \
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$(generated_dir)/memdessertMemDessert.v \
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$(base_dir)/vsrc/const.vh \
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$(base_dir)/vsrc/rocketTestHarness.v \
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$(base_dir)/vsrc/bram_mem.v \
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# C sources
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sim_csrcs = \
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$(base_dir)/csrc/vcs_main.cc \
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$(base_dir)/csrc/mm.cc \
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$(base_dir)/csrc/mm_dramsim2.cc \
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#--------------------------------------------------------------------
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# Build rules
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#--------------------------------------------------------------------
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VCS = vcs -full64
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VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -timescale=1ns/10ps -quiet \
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+rad +v2k +vcs+lic+wait \
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+vc+list -CC "-I$(VCS_HOME)/include" \
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-CC "-I$(RISCV)/include" \
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-CC "-I$(realpath $(base_dir))/dramsim2" \
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-CC "-std=c++11" \
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-CC "-Wl,-rpath,$(RISCV)/lib" \
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-e vcs_main \
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$(RISCV)/lib/libfesvr.so \
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$(sim_dir)/libdramsim.a \
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+define+FPGA \
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+define+TOP=$(FPGAMODEL) \
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+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
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+define+PRINTF_COND=rocketTestHarness.verbose \
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+libext+.v \
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#--------------------------------------------------------------------
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# Build the simulator
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#--------------------------------------------------------------------
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simv = $(sim_dir)/simv
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$(simv) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a
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cd $(sim_dir) && \
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$(VCS) $(VCS_OPTS) -o $(simv) \
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simv_debug = $(sim_dir)/simv-debug
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$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a
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cd $(sim_dir) && \
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$(VCS) $(VCS_OPTS) -o $(simv_debug) \
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+define+DEBUG -debug_pp \
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# +define+MEM_BACKUP_EN \
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#--------------------------------------------------------------------
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# Run
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#--------------------------------------------------------------------
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seed = $(shell date +%s)
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exec_simv = $(simv) -q +ntb_random_seed_automatic
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exec_simv_debug = $(simv_debug) -q +ntb_random_seed_automatic
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