270 lines
6.5 KiB
Scala
270 lines
6.5 KiB
Scala
package rocket
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import Chisel._
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import Node._
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import scala.math._
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object foldR
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{
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def apply[T <: Bits](x: Seq[T])(f: (T, T) => T): T =
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if (x.length == 1) x(0) else f(x(0), foldR(x.slice(1, x.length))(f))
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}
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object log2up
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{
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def apply(in: Int) = ceil(log(in)/log(2)).toInt
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}
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object ispow2
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{
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def apply(in: Int) = in > 0 && ((in & (in-1)) == 0)
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}
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object FillInterleaved
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{
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def apply(n: Int, in: Bits) =
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{
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var out = Fill(n, in(0))
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for (i <- 1 until in.getWidth)
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out = Cat(Fill(n, in(i)), out)
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out
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}
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}
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// http://aggregate.ee.engr.uky.edu/MAGIC/#Population%20Count%20%28Ones%20Count%29
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// http://bits.stephan-brumme.com/countBits.html
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object PopCount
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{
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def apply(in: Bits) =
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{
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require(in.width <= 32)
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val w = log2up(in.width+1)
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var x = in
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if(in.width == 2) {
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x = x - ((x >> UFix(1)) & Bits("h_5555_5555"))
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} else if(in.width <= 4) {
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x = x - ((x >> UFix(1)) & Bits("h_5555_5555"))
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x = (((x >> UFix(2)) & Bits("h_3333_3333")) + (x & Bits("h_3333_3333")))
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} else if(in.width <= 8) {
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x = x - ((x >> UFix(1)) & Bits("h_5555_5555"))
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x = (((x >> UFix(2)) & Bits("h_3333_3333")) + (x & Bits("h_3333_3333")))
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x = ((x >> UFix(4)) + x)
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} else {
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// count bits of each 2-bit chunk
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x = x - ((x >> UFix(1)) & Bits("h_5555_5555"))
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// count bits of each 4-bit chunk
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x = (((x >> UFix(2)) & Bits("h_3333_3333")) + (x & Bits("h_3333_3333")))
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// count bits of each 8-bit chunk
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x = ((x >> UFix(4)) + x)
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// mask junk in upper bits
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x = x & Bits("h_0f0f_0f0f")
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// add all four 8-bit chunks
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x = x + (x >> UFix(8))
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x = x + (x >> UFix(16))
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}
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x(w-1,0)
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}
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}
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object Reverse
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{
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def apply(in: Bits) =
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{
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var out = in(in.getWidth-1)
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for (i <- 1 until in.getWidth)
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out = Cat(in(in.getWidth-i-1), out)
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out
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}
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}
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object OHToUFix
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{
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def apply(in: Bits): UFix =
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{
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val out = MuxCase( UFix(0), (0 until in.getWidth).map( i => (in(i).toBool, UFix(i))))
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out.toUFix
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}
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def apply(in: Seq[Bool]): UFix =
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{
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val out = MuxCase( UFix(0), in.zipWithIndex map {case (b,i) => (b, UFix(i))})
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out.toUFix
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}
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}
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object UFixToOH
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{
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def apply(in: UFix, width: Int): Bits =
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{
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(UFix(1) << in(log2up(width)-1,0))
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}
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}
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object LFSR16
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{
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def apply(increment: Bool = Bool(true)) =
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{
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val width = 16
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val lfsr = Reg(resetVal = UFix(1, width))
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when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)).toUFix }
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lfsr
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}
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}
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object ShiftRegister
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{
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def apply [T <: Data](n: Int, in: T): T =
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if (n > 0) Reg(apply(n-1, in)) else in
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}
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object Mux1H
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{
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//TODO: cloning in(0) is unsafe if other elements have different widths, but
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//is that even allowable?
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def apply [T <: Data](n: Int, sel: Vec[Bool], in: Vec[T]): T = {
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MuxCase(in(0), (0 until n).map( i => (sel(i), in(i))))
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// val mux = (new Mux1H(n)){ in(0).clone }
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// mux.io.sel <> sel
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// mux.io.in <> in
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// mux.io.out.asInstanceOf[T]
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}
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def apply [T <: Data](n: Int, sel: Seq[Bool], in: Vec[T]): T = {
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MuxCase(in(0), (0 until n).map( i => (sel(i), in(i))))
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// val mux = (new Mux1H(n)){ in(0).clone }
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// for(i <- 0 until n) {
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// mux.io.sel(i) := sel(i)
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// }
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// mux.io.in <> in.asOutput
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// mux.io.out.asInstanceOf[T]
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}
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def apply [T <: Data](n: Int, sel: Bits, in: Vec[T]): T = {
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MuxCase(in(0), (0 until n).map( i => (sel(i).toBool, in(i))))
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// val mux = (new Mux1H(n)){ in(0).clone }
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// for(i <- 0 until n) {
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// mux.io.sel(i) := sel(i).toBool
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// }
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// mux.io.in := in
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// mux.io.out
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}
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}
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class Mux1H [T <: Data](n: Int)(gen: => T) extends Component
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{
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val io = new Bundle {
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val sel = Vec(n) { Bool(dir = INPUT) }
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val in = Vec(n) { gen }.asInput
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val out = gen.asOutput
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}
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def buildMux(sel: Bits, in: Vec[T], i: Int, n: Int): T = {
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if (n == 1)
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in(i)
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else
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{
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val half_n = (1 << log2up(n))/2
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val left = buildMux(sel, in, i, half_n)
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val right = buildMux(sel, in, i + half_n, n - half_n)
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Mux(sel(i+n-1,i+half_n).orR, right, left)
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}
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}
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io.out := buildMux(io.sel.toBits, io.in, 0, n)
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}
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class ioDecoupled[+T <: Data]()(data: => T) extends Bundle
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{
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val ready = Bool(INPUT)
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val valid = Bool(OUTPUT)
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val bits = data.asOutput
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}
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class ioPipe[+T <: Data]()(data: => T) extends Bundle
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{
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val valid = Bool(OUTPUT)
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val bits = data.asOutput
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}
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class ioArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
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val in = Vec(n) { (new ioDecoupled()) { data } }.flip
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val out = (new ioDecoupled()) { data }
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}
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class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
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val io = new ioArbiter(n)(data)
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io.in(0).ready := io.out.ready
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for (i <- 1 to n-1) {
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io.in(i).ready := !io.in(i-1).valid && io.in(i-1).ready
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}
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var dout = io.in(n-1).bits
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for (i <- 1 to n-1)
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dout = Mux(io.in(n-1-i).valid, io.in(n-1-i).bits, dout)
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var vout = io.in(0).valid
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for (i <- 1 to n-1)
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vout = vout || io.in(i).valid
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vout <> io.out.valid
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dout <> io.out.bits
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}
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class ioLockingArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
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val in = Vec(n) { (new ioDecoupled()) { data } }.flip
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val lock = Vec(n) { Bool() }.asInput
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val out = (new ioDecoupled()) { data }
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}
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class LockingArbiter[T <: Data](n: Int)(data: => T) extends Component {
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val io = new ioLockingArbiter(n)(data)
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val locked = Vec(n) { Reg(resetVal = Bool(false)) }
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var dout = io.in(0).bits
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var vout = Bool(false)
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for (i <- 0 until n) {
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io.in(i).ready := io.out.ready
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}
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val any_lock_held = (locked.toBits & io.lock.toBits).orR
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when(any_lock_held) {
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vout = io.in(0).valid && locked(0)
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for (i <- 0 until n) {
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io.in(i).ready := io.out.ready && locked(i)
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dout = Mux(locked(i), io.in(i).bits, dout)
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vout = vout || io.in(i).valid && locked(i)
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}
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} .otherwise {
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io.in(0).ready := io.out.ready
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locked(0) := io.out.ready && io.lock(0)
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for (i <- 1 until n) {
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io.in(i).ready := !io.in(i-1).valid && io.in(i-1).ready
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locked(i) := !io.in(i-1).valid && io.in(i-1).ready && io.lock(i)
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}
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dout = io.in(n-1).bits
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for (i <- 1 until n)
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dout = Mux(io.in(n-1-i).valid, io.in(n-1-i).bits, dout)
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vout = io.in(0).valid
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for (i <- 1 until n)
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vout = vout || io.in(i).valid
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}
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vout <> io.out.valid
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dout <> io.out.bits
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}
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object PriorityEncoder
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{
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def apply(in: Bits): UFix = doApply(in, 0)
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def doApply(in: Bits, n: Int = 0): UFix = {
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if (n >= in.getWidth-1)
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UFix(n)
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else
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Mux(in(n), UFix(n), doApply(in, n+1))
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}
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}
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