Megan Wachs dd4a50c452 Add JTAG DTM and test support in simulation ... Initial cut checkpoint which compiles and runs but there is some off-by-1 in the protocol Debugging the clock crossing logic checkpoint which works Clean up the AsyncMailbox black box		2016-08-19 16:08:17 -07:00
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.gitignore	Write test harness in Chisel	2016-08-15 23:27:27 -07:00
Makefile	Write test harness in Chisel	2016-08-15 23:27:27 -07:00
Makefrag	Add JTAG DTM and test support in simulation	2016-08-19 16:08:17 -07:00
Makefrag-verilog	Write test harness in Chisel	2016-08-15 23:27:27 -07:00
vlsi_mem_gen	Massive update containing several months of changes from the now-defunct private chip repo.	2015-07-02 14:43:30 -07:00