122 lines
3.8 KiB
Scala
122 lines
3.8 KiB
Scala
package uncore.devices
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import uncore.tilelink._
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import HastiConstants._
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class BRAMSlave(depth: Int)(implicit val p: Parameters) extends Module
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with HasTileLinkParameters {
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val io = new ClientUncachedTileLinkIO().flip
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val bram = SeqMem(depth, Vec(tlDataBytes, UInt(width = 8)))
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val s_idle :: s_getblk :: s_putblk :: s_resp :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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val acq = io.acquire.bits
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val r_acq = Reg(new AcquireMetadata)
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val (is_get :: is_getblk :: is_put :: is_putblk :: Nil) = Seq(
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Acquire.getType, Acquire.getBlockType, Acquire.putType, Acquire.putBlockType
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).map(acq.isBuiltInType _)
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val beats = Reg(UInt(width = tlBeatAddrBits))
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when (io.acquire.fire()) {
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r_acq := acq
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when (is_get || is_put || acq.isPrefetch()) {
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state := s_resp
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}
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when (is_getblk) {
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beats := UInt(tlDataBeats - 1)
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state := s_getblk
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}
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/** Need to collect the rest of the beats.
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* Beat 0 has already been accepted. */
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when (is_putblk) {
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beats := UInt(tlDataBeats - 2)
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state := s_putblk
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}
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}
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when (state === s_getblk && io.grant.ready) {
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r_acq.addr_beat := r_acq.addr_beat + UInt(1)
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beats := beats - UInt(1)
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when (beats === UInt(0)) { state := s_idle }
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}
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when (state === s_putblk && io.acquire.valid) {
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beats := beats - UInt(1)
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when (beats === UInt(0)) { state := s_resp }
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}
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when (state === s_resp && io.grant.ready) { state := s_idle }
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val acq_addr = Cat(acq.addr_block, acq.addr_beat)
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val r_acq_addr = Cat(r_acq.addr_block, r_acq.addr_beat)
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val ren = (io.acquire.fire() && (is_get || is_getblk)) ||
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(state === s_getblk && io.grant.ready)
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val raddr = Mux(state === s_idle, acq_addr,
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Mux(io.grant.ready, r_acq_addr + UInt(1), r_acq_addr))
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val rdata = bram.read(raddr, ren)
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val wen = (io.acquire.fire() && (is_put || is_putblk))
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val wdata = Vec.tabulate(tlDataBytes) { i => acq.data((i+1)*8-1, i*8) }
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val wmask = Vec.tabulate(tlWriteMaskBits) { i => acq.wmask()(i) }
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when (wen) { bram.write(acq_addr, wdata, wmask) }
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io.grant.valid := (state === s_resp) || (state === s_getblk)
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io.grant.bits := Grant(
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is_builtin_type = Bool(true),
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g_type = r_acq.getBuiltInGrantType(),
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client_xact_id = r_acq.client_xact_id,
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manager_xact_id = UInt(0),
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addr_beat = r_acq.addr_beat,
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data = rdata.toBits)
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io.acquire.ready := (state === s_idle) || (state === s_putblk)
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}
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class HastiRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p) {
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val io = new HastiSlaveIO
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val wdata = Vec.tabulate(hastiDataBytes)(i => io.hwdata(8*(i+1)-1,8*i))
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val waddr = Reg(UInt(width = hastiAddrBits))
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val wvalid = Reg(init = Bool(false))
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val wsize = Reg(UInt(width = SZ_HSIZE))
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val ram = SeqMem(depth, Vec(hastiDataBytes, Bits(width = 8)))
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val max_size = log2Ceil(hastiDataBytes)
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val wmask_lut = MuxLookup(wsize, SInt(-1, hastiDataBytes).asUInt,
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(0 until max_size).map(sz => (UInt(sz) -> UInt((1 << (1 << sz)) - 1))))
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val wmask = (wmask_lut << waddr(max_size - 1, 0))(hastiDataBytes - 1, 0)
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val is_trans = io.hsel && (io.htrans === HTRANS_NONSEQ || io.htrans === HTRANS_SEQ)
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val raddr = io.haddr >> UInt(max_size)
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val ren = is_trans && !io.hwrite
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val bypass = Reg(init = Bool(false))
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when (is_trans && io.hwrite) {
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waddr := io.haddr
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wsize := io.hsize
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wvalid := Bool(true)
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} .otherwise { wvalid := Bool(false) }
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when (ren) { bypass := wvalid && (waddr >> UInt(max_size)) === raddr }
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when (wvalid) {
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ram.write(waddr >> UInt(max_size), wdata, wmask.toBools)
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}
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val rdata = ram.read(raddr, ren)
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io.hrdata := Cat(rdata.zip(wmask.toBools).zip(wdata).map {
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case ((rbyte, wsel), wbyte) => Mux(wsel && bypass, wbyte, rbyte)
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}.reverse)
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io.hready := Bool(true)
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io.hresp := HRESP_OKAY
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}
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