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rocket-chip
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6ea35125d4442e6587ba1c8c26e211780f5ad91f
rocket-chip
/
src
/
main
/
scala
T
History
Wesley W. Terpstra
9153a9a733
ClockDivider: add docs to appease the reviewer
...
... even though this means a delay of 1:30 hours :(
2017-02-17 19:35:08 +01:00
..
config
Configs: use a uniform syntax without Match exceptions (
#507
)
2017-01-13 14:41:19 -08:00
coreplex
coreplex: assume L1 runs no slower than L2
2017-02-17 15:15:41 +01:00
diplomacy
Add externalIn and externalOut property to Nodes that indicates whether the edges are external or not. (
#554
)
2017-02-10 10:19:22 -08:00
groundtest
Heterogeneous Tiles (
#550
)
2017-02-09 13:59:09 -08:00
junctions
rocketchip: work-around
ucb-bar/chisel3#472
2017-01-31 14:20:02 -08:00
regmapper
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
rocket
coreplex: assume L1 runs no slower than L2
2017-02-17 15:15:41 +01:00
rocketchip
build: support waveform debug using opensource tools
2017-02-17 03:38:17 +01:00
tile
Heterogeneous Tiles (
#550
)
2017-02-09 13:59:09 -08:00
uncore
TLRational: test all corners
2017-02-17 14:44:31 +01:00
unittest
Artefact output (
#545
)
2017-02-02 19:24:55 -08:00
util
ClockDivider: add docs to appease the reviewer
2017-02-17 19:35:08 +01:00