e8c8d2af71
Fundamental new features: * Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces. * Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile. * Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile. * Defined RocketCoreParams: All the parameters that can be varied per-core. * Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes. * Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created. * Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little. * Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support. Additional changes that got rolled in along the way: * rocket: Fix critical path through BTB for I$ index bits > pgIdxBits * coreplex: tiles connected via :=* * groundtest: updated to use TileParams * tilelink: cache cork requirements are relaxed to allow more cacheless masters
62 lines
1.3 KiB
Scala
62 lines
1.3 KiB
Scala
// See LICENSE.Berkeley for license details.
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package rocket
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package constants
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import Chisel._
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import scala.math._
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trait ScalarOpConstants {
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val MT_SZ = 3
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def MT_X = BitPat("b???")
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def MT_B = UInt("b000")
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def MT_H = UInt("b001")
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def MT_W = UInt("b010")
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def MT_D = UInt("b011")
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def MT_BU = UInt("b100")
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def MT_HU = UInt("b101")
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def MT_WU = UInt("b110")
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def mtSize(mt: UInt) = mt(MT_SZ-2, 0)
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def mtSigned(mt: UInt) = !mt(MT_SZ-1)
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val SZ_BR = 3
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def BR_X = BitPat("b???")
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def BR_EQ = UInt(0, 3)
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def BR_NE = UInt(1, 3)
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def BR_J = UInt(2, 3)
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def BR_N = UInt(3, 3)
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def BR_LT = UInt(4, 3)
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def BR_GE = UInt(5, 3)
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def BR_LTU = UInt(6, 3)
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def BR_GEU = UInt(7, 3)
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def A1_X = BitPat("b??")
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def A1_ZERO = UInt(0, 2)
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def A1_RS1 = UInt(1, 2)
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def A1_PC = UInt(2, 2)
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def IMM_X = BitPat("b???")
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def IMM_S = UInt(0, 3)
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def IMM_SB = UInt(1, 3)
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def IMM_U = UInt(2, 3)
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def IMM_UJ = UInt(3, 3)
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def IMM_I = UInt(4, 3)
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def IMM_Z = UInt(5, 3)
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def A2_X = BitPat("b??")
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def A2_ZERO = UInt(0, 2)
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def A2_SIZE = UInt(1, 2)
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def A2_RS2 = UInt(2, 2)
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def A2_IMM = UInt(3, 2)
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def X = BitPat("b?")
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def N = BitPat("b0")
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def Y = BitPat("b1")
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val SZ_DW = 1
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def DW_X = X
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def DW_32 = Bool(false)
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def DW_64 = Bool(true)
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def DW_XPR = DW_64
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}
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