144 lines
4.8 KiB
Scala
144 lines
4.8 KiB
Scala
// See LICENSE for license details.
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package rocket
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import Chisel._
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import ALU._
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import Util._
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class MultiplierReq extends CoreBundle {
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val fn = Bits(width = SZ_ALU_FN)
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val dw = Bits(width = SZ_DW)
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val in1 = Bits(width = xLen)
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val in2 = Bits(width = xLen)
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val tag = UInt(width = log2Up(params(NMultXpr)))
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}
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class MultiplierResp extends CoreBundle {
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val data = Bits(width = xLen)
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val tag = UInt(width = log2Up(params(NMultXpr)))
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}
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class MultiplierIO extends Bundle {
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val req = Decoupled(new MultiplierReq).flip
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val kill = Bool(INPUT)
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val resp = Decoupled(new MultiplierResp)
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}
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class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false) extends Module {
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val io = new MultiplierIO
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val w = io.req.bits.in1.getWidth
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val mulw = (w+mulUnroll-1)/mulUnroll*mulUnroll
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val s_ready :: s_neg_inputs :: s_busy :: s_move_rem :: s_neg_output :: s_done :: Nil = Enum(UInt(), 6)
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val state = Reg(init=s_ready)
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val req = Reg(io.req.bits)
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val count = Reg(UInt(width = log2Up(w+1)))
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val neg_out = Reg(Bool())
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val isMul = Reg(Bool())
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val isHi = Reg(Bool())
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val divisor = Reg(Bits(width = w+1)) // div only needs w bits
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val remainder = Reg(Bits(width = 2*mulw+2)) // div only needs 2*w+1 bits
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val cmdMul :: cmdHi :: lhsSigned :: rhsSigned :: Nil =
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DecodeLogic(io.req.bits.fn, List(X, X, X, X), List(
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FN_DIV -> List(N, N, Y, Y),
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FN_REM -> List(N, Y, Y, Y),
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FN_DIVU -> List(N, N, N, N),
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FN_REMU -> List(N, Y, N, N),
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FN_MUL -> List(Y, N, X, X),
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FN_MULH -> List(Y, Y, Y, Y),
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FN_MULHU -> List(Y, Y, N, N),
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FN_MULHSU -> List(Y, Y, Y, N)))
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def sext(x: Bits, signed: Bool) = {
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val sign = signed && Mux(io.req.bits.dw === DW_64, x(w-1), x(w/2-1))
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val hi = Mux(io.req.bits.dw === DW_64, x(w-1,w/2), Fill(w/2, sign))
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(Cat(hi, x(w/2-1,0)), sign)
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}
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val (lhs_in, lhs_sign) = sext(io.req.bits.in1, lhsSigned)
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val (rhs_in, rhs_sign) = sext(io.req.bits.in2, rhsSigned)
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val subtractor = remainder(2*w,w) - divisor(w,0)
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val less = subtractor(w)
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val negated_remainder = -remainder(w-1,0)
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when (state === s_neg_inputs) {
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when (remainder(w-1) || isMul) {
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remainder := negated_remainder
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}
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when (divisor(w-1) || isMul) {
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divisor := subtractor
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}
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state := s_busy
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}
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when (state === s_neg_output) {
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remainder := negated_remainder
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state := s_done
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}
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when (state === s_move_rem) {
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remainder := remainder(2*w, w+1)
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state := Mux(neg_out, s_neg_output, s_done)
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}
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when (state === s_busy && isMul) {
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val mulReg = Cat(remainder(2*mulw+1,w+1),remainder(w-1,0))
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val mplier = mulReg(mulw-1,0)
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val accum = mulReg(2*mulw,mulw).toSInt
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val mpcand = divisor.toSInt
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val prod = mplier(mulUnroll-1,0) * mpcand + accum
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val nextMulReg = Cat(prod, mplier(mulw-1,mulUnroll)).toUInt
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val eOutMask = (SInt(BigInt(-1) << mulw) >> (count * mulUnroll)(log2Up(mulw)-1,0))(mulw-1,0)
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val eOut = Bool(earlyOut) && count != mulw/mulUnroll-1 && count != 0 &&
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!isHi && (mplier & ~eOutMask) === UInt(0)
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val eOutRes = (mulReg >> (mulw - count * mulUnroll)(log2Up(mulw)-1,0))
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val nextMulReg1 = Cat(nextMulReg(2*mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0))
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remainder := Cat(nextMulReg1 >> w, Bool(false), nextMulReg1(w-1,0)).toSInt
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count := count + 1
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when (eOut || count === mulw/mulUnroll-1) {
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state := Mux(isHi, s_move_rem, s_done)
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}
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}
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when (state === s_busy && !isMul) {
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when (count === w) {
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state := Mux(isHi, s_move_rem, Mux(neg_out, s_neg_output, s_done))
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}
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count := count + 1
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remainder := Cat(Mux(less, remainder(2*w-1,w), subtractor(w-1,0)), remainder(w-1,0), !less)
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val divisorMSB = Log2(divisor(w-1,0), w)
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val dividendMSB = Log2(remainder(w-1,0), w)
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val eOutPos = UInt(w-1) + divisorMSB - dividendMSB
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val eOutZero = divisorMSB > dividendMSB
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val eOut = count === 0 && less /* not divby0 */ && (eOutPos > 0 || eOutZero)
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when (Bool(earlyOut) && eOut) {
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val shift = Mux(eOutZero, UInt(w-1), eOutPos(log2Up(w)-1,0))
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remainder := remainder(w-1,0) << shift
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count := shift
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}
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when (count === 0 && !less /* divby0 */ && !isHi) { neg_out := false }
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}
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when (io.resp.fire() || io.kill) {
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state := s_ready
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}
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when (io.req.fire()) {
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state := Mux(lhs_sign || rhs_sign && !cmdMul, s_neg_inputs, s_busy)
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isMul := cmdMul
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isHi := cmdHi
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count := 0
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neg_out := !cmdMul && Mux(cmdHi, lhs_sign, lhs_sign != rhs_sign)
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divisor := Cat(rhs_sign, rhs_in)
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remainder := lhs_in
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req := io.req.bits
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}
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io.resp.bits := req
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io.resp.bits.data := Mux(req.dw === DW_32, Cat(Fill(w/2, remainder(w/2-1)), remainder(w/2-1,0)), remainder(w-1,0))
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io.resp.valid := state === s_done
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io.req.ready := state === s_ready
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}
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