95 lines
2.6 KiB
Scala
95 lines
2.6 KiB
Scala
// See LICENSE for license details.
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package rocket
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import Chisel._
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import Util._
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import uncore._
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case object BuildFPU extends Field[Option[() => FPU]]
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case object FDivSqrt extends Field[Boolean]
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case object XLen extends Field[Int]
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case object NMultXpr extends Field[Int]
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case object FetchWidth extends Field[Int]
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case object RetireWidth extends Field[Int]
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case object UseVM extends Field[Boolean]
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case object FastLoadWord extends Field[Boolean]
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case object FastLoadByte extends Field[Boolean]
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case object FastMulDiv extends Field[Boolean]
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case object CoreInstBits extends Field[Int]
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case object CoreDataBits extends Field[Int]
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case object CoreDCacheReqTagBits extends Field[Int]
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case object NCustomMRWCSRs extends Field[Int]
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abstract trait CoreParameters extends UsesParameters {
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val xLen = params(XLen)
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val paddrBits = params(PAddrBits)
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val vaddrBits = params(VAddrBits)
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val pgIdxBits = params(PgIdxBits)
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val ppnBits = params(PPNBits)
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val vpnBits = params(VPNBits)
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val pgLevels = params(PgLevels)
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val pgLevelBits = params(PgLevelBits)
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val asIdBits = params(ASIdBits)
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val retireWidth = params(RetireWidth)
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val coreFetchWidth = params(FetchWidth)
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val coreInstBits = params(CoreInstBits)
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val coreInstBytes = coreInstBits/8
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val coreDataBits = xLen
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val coreDataBytes = coreDataBits/8
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val coreDCacheReqTagBits = params(CoreDCacheReqTagBits)
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val coreMaxAddrBits = math.max(ppnBits,vpnBits+1) + pgIdxBits
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val vaddrBitsExtended = vaddrBits + (vaddrBits < xLen).toInt
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if(params(FastLoadByte)) require(params(FastLoadWord))
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}
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abstract trait RocketCoreParameters extends CoreParameters
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{
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require(params(FetchWidth) == 1) // for now...
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require(params(RetireWidth) == 1) // for now...
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}
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abstract class CoreBundle extends Bundle with CoreParameters
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abstract class CoreModule extends Module with CoreParameters
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class RocketIO extends Bundle
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{
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val host = new HTIFIO
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val imem = new CPUFrontendIO
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val dmem = new HellaCacheIO
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val ptw = new DatapathPTWIO().flip
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val rocc = new RoCCInterface().flip
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}
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class Core extends Module with CoreParameters
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{
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val io = new RocketIO
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val ctrl = Module(new Control)
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val dpath = Module(new Datapath)
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//If so specified, build an FPU module and wire it in
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params(BuildFPU)
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.map { bf => bf() }
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.foreach { fpu =>
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dpath.io.fpu <> fpu.io.dpath
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ctrl.io.fpu <> fpu.io.ctrl
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}
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ctrl.io.dpath <> dpath.io.ctrl
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dpath.io.host <> io.host
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ctrl.io.imem <> io.imem
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dpath.io.imem <> io.imem
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ctrl.io.dmem <> io.dmem
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dpath.io.dmem <> io.dmem
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dpath.io.ptw <> io.ptw
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ctrl.io.rocc <> io.rocc
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dpath.io.rocc <> io.rocc
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}
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