243 lines
8.9 KiB
Scala
243 lines
8.9 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.devices.tilelink
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import Chisel._
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import Chisel.ImplicitConversions._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.coreplex.{HasInterruptBus, HasPeripheryBus}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tile.XLen
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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import scala.math.min
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class GatewayPLICIO extends Bundle {
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val valid = Bool(OUTPUT)
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val ready = Bool(INPUT)
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val complete = Bool(INPUT)
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}
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class LevelGateway extends Module {
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val io = new Bundle {
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val interrupt = Bool(INPUT)
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val plic = new GatewayPLICIO
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}
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val inFlight = Reg(init=Bool(false))
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when (io.interrupt && io.plic.ready) { inFlight := true }
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when (io.plic.complete) { inFlight := false }
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io.plic.valid := io.interrupt && !inFlight
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}
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object PLICConsts
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{
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def maxDevices = 1023
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def maxHarts = 15872
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def priorityBase = 0x0
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def pendingBase = 0x1000
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def enableBase = 0x2000
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def hartBase = 0x200000
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def claimOffset = 4
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def priorityBytes = 4
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def enableOffset(i: Int) = i * ((maxDevices+7)/8)
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def hartOffset(i: Int) = i * 0x1000
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def enableBase(i: Int):Int = enableOffset(i) + enableBase
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def hartBase(i: Int):Int = hartOffset(i) + hartBase
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def size = hartBase(maxHarts)
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require(hartBase >= enableBase(maxHarts))
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}
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case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0)
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{
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require (maxPriorities >= 0)
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def address = AddressSet(baseAddress, PLICConsts.size-1)
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}
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case object PLICKey extends Field(PLICParams())
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/** Platform-Level Interrupt Controller */
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class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
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{
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// plic0 => max devices 1023
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val device = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) {
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override val alwaysExtended = true
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override def describe(resources: ResourceBindings): Description = {
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val Description(name, mapping) = super.describe(resources)
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val extra = Map(
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"interrupt-controller" -> Nil,
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"riscv,ndev" -> Seq(ResourceInt(nDevices)),
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"riscv,max-priority" -> Seq(ResourceInt(params.maxPriorities)),
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"#interrupt-cells" -> Seq(ResourceInt(1)))
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Description(name, mapping ++ extra)
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}
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}
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val node = TLRegisterNode(
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address = Seq(params.address),
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device = device,
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beatBytes = p(XLen)/8,
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undefZero = true,
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concurrency = 1) // limiting concurrency handles RAW hazards on claim registers
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val intnode = IntNexusNode(
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numSourcePorts = 0 to 1024,
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numSinkPorts = 0 to 1024,
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sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) },
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sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) })
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/* Negotiated sizes */
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def nDevices: Int = intnode.edges.in.map(_.source.num).sum
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def nPriorities = min(params.maxPriorities, nDevices)
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def nHarts = intnode.edges.out.map(_.source.num).sum
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// Assign all the devices unique ranges
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lazy val sources = intnode.edges.in.map(_.source)
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lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map {
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case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
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}.flatten
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ResourceBinding {
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flatSources.foreach { s => s.resources.foreach { r =>
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// +1 because interrupt 0 is reserved
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(s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) }
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} }
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}
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lazy val module = new LazyModuleImp(this) {
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val (io_devices, edgesIn) = intnode.in.unzip
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val (io_harts, _) = intnode.out.unzip
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// Compact the interrupt vector the same way
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val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten
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// This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence
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val harts = io_harts.flatten
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println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):")
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flatSources.foreach { s =>
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// +1 because 0 is reserved, +1-1 because the range is half-open
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println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}")
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}
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println("")
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require (nDevices == interrupts.size)
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require (nHarts == harts.size)
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require(nDevices <= PLICConsts.maxDevices)
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require(nHarts > 0 && nHarts <= PLICConsts.maxHarts)
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// For now, use LevelGateways for all TL2 interrupts
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val gateways = Vec((false.B +: interrupts).map { case i =>
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val gateway = Module(new LevelGateway)
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gateway.io.interrupt := i
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gateway.io.plic
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})
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val priority =
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if (nPriorities > 0) Reg(Vec(nDevices+1, UInt(width=log2Up(nPriorities+1))))
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else Wire(init=Vec.fill(nDevices+1)(UInt(1)))
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val threshold =
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if (nPriorities > 0) Reg(Vec(nHarts, UInt(width = log2Up(nPriorities+1))))
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else Wire(init=Vec.fill(nHarts)(UInt(0)))
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val pending = Reg(init=Vec.fill(nDevices+1){Bool(false)})
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val enables = Reg(Vec(nHarts, Vec(nDevices+1, Bool())))
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def findMax(x: Seq[UInt]): (UInt, UInt) = {
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if (x.length > 1) {
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val half = 1 << (log2Ceil(x.length) - 1)
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val left = findMax(x take half)
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val right = findMax(x drop half)
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MuxT(left._1 >= right._1, left, (right._1, UInt(half) | right._2))
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} else (x.head, UInt(0))
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}
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val maxDevs = Reg(Vec(nHarts, UInt(width = log2Up(pending.size))))
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for (hart <- 0 until nHarts) {
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val effectivePriority = (UInt(1) << priority(0).getWidth) +:
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(for (((p, en), pri) <- (pending zip enables(hart) zip priority).tail)
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yield Cat(p && en, pri))
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val (maxPri, maxDev) = findMax(effectivePriority)
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maxDevs(hart) := maxDev
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harts(hart) := ShiftRegister(Reg(next = maxPri) > Cat(UInt(1), threshold(hart)), params.intStages)
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}
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def priorityRegField(x: UInt) = if (nPriorities > 0) RegField(32, x) else RegField.r(32, x)
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val priorityRegFields = Seq(PLICConsts.priorityBase -> priority.map(p => priorityRegField(p)))
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val pendingRegFields = Seq(PLICConsts.pendingBase -> pending .map(b => RegField.r(1, b)))
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val enableRegFields = enables.zipWithIndex.map { case (e, i) =>
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PLICConsts.enableBase(i) -> e.map(b => RegField(1, b))
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}
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// When a hart reads a claim/complete register, then the
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// device which is currently its highest priority is no longer pending.
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// This code exploits the fact that, practically, only one claim/complete
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// register can be read at a time. We check for this because if the address map
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// were to change, it may no longer be true.
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// Note: PLIC doesn't care which hart reads the register.
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val claimer = Wire(Vec(nHarts, Bool()))
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assert((claimer.asUInt & (claimer.asUInt - UInt(1))) === UInt(0)) // One-Hot
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val claiming = Vec.tabulate(nHarts){i => Mux(claimer(i), UIntToOH(maxDevs(i), nDevices+1), UInt(0))}
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val claimedDevs = Vec(claiming.reduceLeft( _ | _ ).toBools)
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((pending zip gateways) zip claimedDevs) foreach { case ((p, g), c) =>
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g.ready := !p
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when (c || g.valid) { p := !c }
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}
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// When a hart writes a claim/complete register, then
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// the written device (as long as it is actually enabled for that
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// hart) is marked complete.
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// This code exploits the fact that, practically, only one claim/complete register
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// can be written at a time. We check for this because if the address map
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// were to change, it may no longer be true.
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// Note -- PLIC doesn't care which hart writes the register.
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val completer = Wire(Vec(nHarts, Bool()))
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assert((completer.asUInt & (completer.asUInt - UInt(1))) === UInt(0)) // One-Hot
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val completerDev = Wire(UInt(width = log2Up(nDevices + 1)))
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val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(completerDev, nDevices+1), UInt(0))
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(gateways zip completedDevs.toBools) foreach { case (g, c) =>
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g.complete := c
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}
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val hartRegFields = Seq.tabulate(nHarts) { i =>
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PLICConsts.hartBase(i) -> Seq(
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priorityRegField(threshold(i)),
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RegField(32,
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RegReadFn { valid =>
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claimer(i) := valid
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(Bool(true), maxDevs(i))
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},
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RegWriteFn { (valid, data) =>
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assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),
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"completerDev should be consistent for all harts")
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completerDev := data.extract(log2Ceil(nDevices+1)-1, 0)
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completer(i) := valid && enables(i)(completerDev)
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Bool(true)
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}
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)
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)
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}
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node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
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priority(0) := 0
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pending(0) := false
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for (e <- enables)
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e(0) := false
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}
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}
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/** Trait that will connect a PLIC to a coreplex */
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trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus {
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val plic = LazyModule(new TLPLIC(p(PLICKey)))
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plic.node := pbus.toVariableWidthSlaves
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plic.intnode := ibus.toPLIC
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}
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