735e4f8ed6
This makes it possible for the bundles to have different widths. Previously, we had to widen all the bundles passing through a node to the widest of all the possibilities. This would mean that if you had two source[] fields, they end up the same.
97 lines
3.6 KiB
Scala
97 lines
3.6 KiB
Scala
// See LICENSE.SiFive for license details.
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package uncore.apb
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import Chisel._
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import config._
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import diplomacy._
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import regmapper._
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import scala.math.{min,max}
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class APBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)
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extends APBSlaveNode(Seq(APBSlavePortParameters(
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Seq(APBSlaveParameters(
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address = Seq(address),
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executable = executable,
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supportsWrite = true,
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supportsRead = true)),
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beatBytes = beatBytes)))
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{
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require (address.contiguous)
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// Calling this method causes the matching APB bundle to be
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// configured to route all requests to the listed RegFields.
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def regmap(mapping: RegField.Map*) = {
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val apb = bundleIn(0)
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val indexBits = log2Up((address.mask+1)/beatBytes)
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val params = RegMapperParams(indexBits, beatBytes, 1)
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val in = Wire(Decoupled(new RegMapperInput(params)))
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val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
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// Only send the request to the RR once
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val taken = RegInit(Bool(false))
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when (in.fire()) { taken := Bool(true) }
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when (out.fire()) { taken := Bool(false) }
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in.bits.read := !apb.pwrite
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in.bits.index := apb.paddr >> log2Ceil(beatBytes)
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in.bits.data := apb.pwdata
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in.bits.mask := Mux(apb.pwrite, apb.pstrb, UInt((1<<beatBytes) - 1))
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in.bits.extra := UInt(0)
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in.valid := apb.psel && !taken
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out.ready := apb.penable
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apb.pready := out.valid
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apb.pslverr := Bool(false)
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apb.prdata := out.bits.data
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}
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}
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object APBRegisterNode
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{
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def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) =
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new APBRegisterNode(address, concurrency, beatBytes, undefZero, executable)
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}
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// These convenience methods below combine to make it possible to create a APB
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// register mapped device from a totally abstract register mapped device.
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abstract class APBRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
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{
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val node = APBRegisterNode(address, concurrency, beatBytes, undefZero, executable)
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val intnode = uncore.tilelink2.IntSourceNode(interrupts)
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}
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case class APBRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[APBBundle])(implicit val p: Parameters)
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class APBRegBundleBase(arg: APBRegBundleArg) extends Bundle
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{
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implicit val p = arg.p
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val interrupts = arg.interrupts
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val in = arg.in
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}
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class APBRegBundle[P](val params: P, arg: APBRegBundleArg) extends APBRegBundleBase(arg)
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class APBRegModule[P, B <: APBRegBundleBase](val params: P, bundleBuilder: => B, router: APBRegisterRouterBase)
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extends LazyModuleImp(router) with HasRegMap
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{
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val io = bundleBuilder
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val interrupts = if (io.interrupts.isEmpty) Vec(0, Bool()) else io.interrupts(0)
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def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
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}
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class APBRegisterRouter[B <: APBRegBundleBase, M <: LazyModuleImp]
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(val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)
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(bundleBuilder: APBRegBundleArg => B)
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(moduleBuilder: (=> B, APBRegisterRouterBase) => M)(implicit p: Parameters)
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extends APBRegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero, executable)
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{
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require (isPow2(size))
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// require (size >= 4096) ... not absolutely required, but highly recommended
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lazy val module = moduleBuilder(bundleBuilder(APBRegBundleArg(intnode.bundleOut, node.bundleIn)), this)
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}
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