4c595d175c
* Refactors package hierarchy. Additionally: - Removes legacy ground tests and configs - Removes legacy bus protocol implementations - Removes NTiles - Adds devices package - Adds more functions to util package
26 lines
853 B
Scala
26 lines
853 B
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.util
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import Chisel._
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class plusarg_reader(val format: String, val default: Int, val docstring: String) extends BlackBox(Map(
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"FORMAT" -> chisel3.core.StringParam(format),
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"DEFAULT" -> chisel3.core.IntParam(default))) {
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val io = new Bundle {
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val out = UInt(OUTPUT, width = 32)
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}
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}
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object PlusArg
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{
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// PlusArg("foo") will return 42.U if the simulation is run with +foo=42
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// Do not use this as an initial register value. The value is set in an
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// initial block and thus accessing it from another initial is racey.
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// Add a docstring to document the arg, which can be dumped in an elaboration
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// pass.
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def apply(name: String, default: Int = 0, docstring: String = ""): UInt =
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Module(new plusarg_reader(name + "=%d", default, docstring)).io.out
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}
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