75 lines
2.5 KiB
Scala
75 lines
2.5 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.devices.tilelink
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.coreplex.HasPeripheryBus
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import scala.math.min
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case class ErrorParams(address: Seq[AddressSet])
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case object ErrorParams extends Field[ErrorParams]
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/** Adds a /dev/null slave that generates TL error response messages */
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class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
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{
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val address = params.address
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val device = new SimpleDevice("error-device", Seq("sifive,error0"))
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val node = TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = address,
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resources = device.reg("mem"),
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supportsGet = TransferSizes(1, beatBytes),
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supportsPutPartial = TransferSizes(1, beatBytes),
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supportsPutFull = TransferSizes(1, beatBytes),
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supportsArithmetic = TransferSizes(1, beatBytes),
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supportsLogical = TransferSizes(1, beatBytes),
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supportsHint = TransferSizes(1, beatBytes),
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fifoId = Some(0))), // requests are handled in order
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beatBytes = beatBytes,
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minLatency = 1))) // no bypass needed for this device
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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}
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import TLMessages._
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val opcodes = Vec(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck)
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val in = io.in(0)
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val a = Queue(in.a, 1)
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val d = in.d
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a.ready := d.ready
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d.valid := a.valid
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d.bits.opcode := opcodes(a.bits.opcode)
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d.bits.param := UInt(0)
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d.bits.size := a.bits.size
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d.bits.source := a.bits.source
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d.bits.sink := UInt(0)
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d.bits.data := UInt(0)
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d.bits.error := a.bits.opcode =/= Hint // Hints may not error
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// Tie off unused channels
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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}
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}
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trait HasPeripheryErrorSlave extends HasPeripheryBus {
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private val params = p(ErrorParams)
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private val maxXfer = min(params.address.map(_.alignment).max.toInt, 4096)
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val error = LazyModule(new TLError(params, pbus.beatBytes))
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// Most slaves do not support a 4kB burst so this slave ends up with many more source bits than others;
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// we exclude the onerously large TLMonitor that results.
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error.node connectButDontMonitor pbus.toLargeBurstSlave(maxXfer)
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}
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