59 lines
1.8 KiB
Scala
59 lines
1.8 KiB
Scala
package coreplex
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import Chisel._
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import config._
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import junctions._
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import diplomacy._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices._
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import uncore.util._
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import uncore.converters._
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import rocket._
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import util._
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trait CoreplexRISCVPlatform extends CoreplexNetwork {
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val module: CoreplexRISCVPlatformModule
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val debug = LazyModule(new TLDebugModule())
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val plic = LazyModule(new TLPLIC(hasSupervisor, maxPriorities = 7))
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val clint = LazyModule(new CoreplexLocalInterrupter)
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debug.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
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plic.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
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clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
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plic.intnode := intBar.intnode
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lazy val configString = {
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val managers = l1tol2.node.edgesIn(0).manager.managers
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rocketchip.GenerateConfigString(p, clint, plic, managers)
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}
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}
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trait CoreplexRISCVPlatformBundle extends CoreplexNetworkBundle {
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val outer: CoreplexRISCVPlatform
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val debug = new AsyncDebugBusIO().flip
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val rtcToggle = Bool(INPUT)
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val resetVector = UInt(INPUT, p(XLen))
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}
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trait CoreplexRISCVPlatformModule extends CoreplexNetworkModule {
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val outer: CoreplexRISCVPlatform
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val io: CoreplexRISCVPlatformBundle
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// Synchronize the debug bus into the coreplex
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outer.debug.module.io.db <> FromAsyncDebugBus(io.debug)
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// Synchronize the rtc into the coreplex
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val rtcSync = ShiftRegister(io.rtcToggle, 3)
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val rtcLast = Reg(init = Bool(false), next=rtcSync)
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outer.clint.module.io.rtcTick := Reg(init = Bool(false), next=(rtcSync & (~rtcLast)))
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println(s"\nGenerated Configuration String\n${outer.configString}")
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ConfigStringOutput.contents = Some(outer.configString)
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}
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