246 lines
8.5 KiB
Scala
246 lines
8.5 KiB
Scala
package rocket
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import Chisel._
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import Node._
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import Constants._
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import scala.math._
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import Util._
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class ioDpathBTB extends Bundle()
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{
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val current_pc = UFix(INPUT, VADDR_BITS);
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val hit = Bool(OUTPUT);
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val target = UFix(OUTPUT, VADDR_BITS);
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val wen = Bool(INPUT);
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val clr = Bool(INPUT);
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val invalidate = Bool(INPUT);
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val correct_pc = UFix(INPUT, VADDR_BITS);
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val correct_target = UFix(INPUT, VADDR_BITS);
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}
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// fully-associative branch target buffer
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class rocketDpathBTB(entries: Int) extends Component
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{
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val io = new ioDpathBTB();
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val repl_way = LFSR16(io.wen)(log2Up(entries)-1,0) // TODO: pseudo-LRU
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var hit_reduction = Bool(false)
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val hit = Bool()
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val update = Bool()
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var update_reduction = Bool(false)
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val hits = Vec(entries) { Bool() }
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val updates = Vec(entries) { Bool() }
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val targets = Vec(entries) { Reg() { UFix() } }
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val anyUpdate = updates.toBits.orR
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for (i <- 0 until entries) {
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val tag = Reg() { UFix() }
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val valid = Reg(resetVal = Bool(false))
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hits(i) := valid && tag === io.current_pc
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updates(i) := valid && tag === io.correct_pc
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when (io.wen && (updates(i) || !anyUpdate && UFix(i) === repl_way)) {
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valid := Bool(false)
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when (!io.clr) {
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valid := Bool(true)
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tag := io.correct_pc
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targets(i) := io.correct_target
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}
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}
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}
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io.hit := hits.toBits.orR
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io.target := Mux1H(hits, targets)
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}
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class ioDpathPCR(implicit conf: RocketConfiguration) extends Bundle
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{
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val host = new ioHTIF(conf.ntiles)
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val r = new ioReadPort(32, 64)
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val w = new ioWritePort(32, 64)
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val status = Bits(OUTPUT, 32);
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val ptbr = UFix(OUTPUT, PADDR_BITS);
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val evec = UFix(OUTPUT, VADDR_BITS);
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val exception = Bool(INPUT);
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val cause = UFix(INPUT, 6);
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val badvaddr_wen = Bool(INPUT);
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val vec_irq_aux = Bits(INPUT, 64)
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val vec_irq_aux_wen = Bool(INPUT)
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val pc = UFix(INPUT, VADDR_BITS+1);
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val eret = Bool(INPUT);
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val ei = Bool(INPUT);
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val di = Bool(INPUT);
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val ptbr_wen = Bool(OUTPUT);
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val irq_timer = Bool(OUTPUT);
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val irq_ipi = Bool(OUTPUT);
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val replay = Bool(OUTPUT)
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val vecbank = Bits(OUTPUT, 8)
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val vecbankcnt = UFix(OUTPUT, 4)
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val vec_appvl = UFix(INPUT, 12)
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val vec_nxregs = UFix(INPUT, 6)
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val vec_nfregs = UFix(INPUT, 6)
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}
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class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component
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{
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val io = new ioDpathPCR
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val reg_epc = Reg{Fix()}
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val reg_badvaddr = Reg{Fix()}
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val reg_ebase = Reg{Fix()}
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val reg_count = WideCounter(32)
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val reg_compare = Reg() { UFix() };
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val reg_cause = Reg() { Bits() };
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val reg_tohost = Reg(resetVal = Bits(0, 64));
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val reg_fromhost = Reg(resetVal = Bits(0, 64));
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val reg_coreid = Reg() { Bits() }
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val reg_k0 = Reg() { Bits() };
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val reg_k1 = Reg() { Bits() };
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val reg_ptbr = Reg() { UFix() };
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val reg_vecbank = Reg(resetVal = Bits("b1111_1111", 8))
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val reg_error_mode = Reg(resetVal = Bool(false));
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val reg_status_vm = Reg(resetVal = Bool(false));
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val reg_status_im = Reg(resetVal = Bits(0,SR_IM_WIDTH));
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val reg_status_sx = Reg(resetVal = Bool(true));
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val reg_status_ux = Reg(resetVal = Bool(true));
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val reg_status_ec = Reg(resetVal = Bool(false));
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val reg_status_ef = Reg(resetVal = Bool(false));
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val reg_status_ev = Reg(resetVal = Bool(false));
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val reg_status_s = Reg(resetVal = Bool(true));
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val reg_status_ps = Reg(resetVal = Bool(false));
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val reg_status_et = Reg(resetVal = Bool(false));
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val r_irq_timer = Reg(resetVal = Bool(false));
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val r_irq_ipi = Reg(resetVal = Bool(true))
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val rdata = Bits();
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val raddr = Mux(io.r.en, io.r.addr, io.host.pcr_req.bits.addr(4,0))
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io.host.pcr_rep.valid := io.host.pcr_req.fire()
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io.host.pcr_rep.bits := rdata
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val wen = io.w.en || !io.r.en && io.host.pcr_req.valid && io.host.pcr_req.bits.rw
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val waddr = Mux(io.w.en, io.w.addr, io.host.pcr_req.bits.addr)
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val wdata = Mux(io.w.en, io.w.data, io.host.pcr_req.bits.data)
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io.host.pcr_req.ready := !io.w.en && !io.r.en
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io.ptbr_wen := reg_status_vm.toBool && wen && (waddr === PCR_PTBR);
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io.status := Cat(reg_status_im, Bits(0,7), reg_status_vm, reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, reg_status_ec, reg_status_ev, reg_status_ef, reg_status_et);
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io.evec := Mux(io.exception, reg_ebase, reg_epc).toUFix
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io.ptbr := reg_ptbr;
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io.host.debug.error_mode := reg_error_mode;
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io.r.data := rdata;
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io.vecbank := reg_vecbank
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var cnt = UFix(0,4)
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for (i <- 0 until 8)
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cnt = cnt + reg_vecbank(i)
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io.vecbankcnt := cnt(3,0)
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val badvaddr_sign = Mux(io.w.data(VADDR_BITS-1), ~io.w.data(63,VADDR_BITS) === UFix(0), io.w.data(63,VADDR_BITS) != UFix(0))
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when (io.badvaddr_wen) {
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reg_badvaddr := Cat(badvaddr_sign, io.w.data(VADDR_BITS-1,0)).toUFix;
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}
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when (io.vec_irq_aux_wen) {
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reg_badvaddr := io.vec_irq_aux.toUFix
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}
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when (io.exception) {
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when (!reg_status_et) {
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reg_error_mode := Bool(true)
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}
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.otherwise {
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reg_status_s := Bool(true);
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reg_status_ps := reg_status_s;
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reg_status_et := Bool(false);
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reg_epc := io.pc;
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reg_cause := io.cause;
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}
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}
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when (io.eret) {
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reg_status_s := reg_status_ps;
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reg_status_et := Bool(true);
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}
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when (reg_count === reg_compare) {
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r_irq_timer := Bool(true);
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}
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io.irq_timer := r_irq_timer;
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io.irq_ipi := r_irq_ipi;
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io.host.ipi_req.valid := io.w.en && io.w.addr === PCR_SEND_IPI
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io.host.ipi_req.bits := io.w.data
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io.replay := io.host.ipi_req.valid && !io.host.ipi_req.ready
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when (io.host.pcr_req.fire() && !io.host.pcr_req.bits.rw && io.host.pcr_req.bits.addr === PCR_TOHOST) { reg_tohost := UFix(0) }
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when (wen) {
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when (waddr === PCR_STATUS) {
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reg_status_vm := wdata(SR_VM).toBool;
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reg_status_im := wdata(SR_IM_WIDTH+SR_IM,SR_IM);
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reg_status_sx := wdata(SR_S64).toBool;
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reg_status_ux := wdata(SR_U64).toBool;
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reg_status_s := wdata(SR_S).toBool;
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reg_status_ps := wdata(SR_PS).toBool;
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reg_status_ev := Bool(conf.vec) && wdata(SR_EV).toBool;
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reg_status_ef := Bool(conf.fpu) && wdata(SR_EF).toBool;
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reg_status_ec := Bool(conf.rvc) && wdata(SR_EC).toBool;
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reg_status_et := wdata(SR_ET).toBool;
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}
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when (waddr === PCR_EPC) { reg_epc := wdata(VADDR_BITS,0).toFix }
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when (waddr === PCR_EVEC) { reg_ebase := wdata(VADDR_BITS-1,0).toUFix; }
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when (waddr === PCR_COUNT) { reg_count := wdata.toUFix }
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when (waddr === PCR_COMPARE) { reg_compare := wdata(31,0).toUFix; r_irq_timer := Bool(false); }
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when (waddr === PCR_COREID) { reg_coreid := wdata(15,0) }
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when (waddr === PCR_FROMHOST) { when (reg_fromhost === UFix(0) || io.w.en) { reg_fromhost := wdata } }
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when (waddr === PCR_TOHOST) { when (reg_tohost === UFix(0)) { reg_tohost := wdata } }
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when (waddr === PCR_CLR_IPI) { r_irq_ipi := wdata(0) }
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when (waddr === PCR_K0) { reg_k0 := wdata; }
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when (waddr === PCR_K1) { reg_k1 := wdata; }
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when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
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when (waddr === PCR_VECBANK) { reg_vecbank:= wdata(7,0) }
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}
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io.host.ipi_rep.ready := Bool(true)
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when (io.host.ipi_rep.valid) { r_irq_ipi := Bool(true) }
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rdata := io.status // raddr === PCR_STATUS
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switch (raddr) {
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is (PCR_EPC) { rdata := reg_epc }
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is (PCR_BADVADDR) { rdata := reg_badvaddr }
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is (PCR_EVEC) { rdata := reg_ebase }
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is (PCR_COUNT) { rdata := reg_count }
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is (PCR_COMPARE) { rdata := reg_compare }
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is (PCR_CAUSE) { rdata := reg_cause(5) << 63 | reg_cause(4,0) }
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is (PCR_COREID) { rdata := reg_coreid }
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is (PCR_IMPL) { rdata := Bits(2) }
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is (PCR_FROMHOST) { rdata := reg_fromhost; }
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is (PCR_TOHOST) { rdata := reg_tohost; }
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is (PCR_K0) { rdata := reg_k0; }
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is (PCR_K1) { rdata := reg_k1; }
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is (PCR_PTBR) { rdata := reg_ptbr }
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is (PCR_VECBANK) { rdata := Cat(Bits(0, 56), reg_vecbank) }
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is (PCR_VECCFG) { rdata := Cat(Bits(0, 40), io.vec_nfregs, io.vec_nxregs, io.vec_appvl) }
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}
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}
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class ioReadPort(d: Int, w: Int) extends Bundle
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{
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val addr = UFix(INPUT, log2Up(d))
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val en = Bool(INPUT)
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val data = Bits(OUTPUT, w)
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override def clone = new ioReadPort(d, w).asInstanceOf[this.type]
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}
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class ioWritePort(d: Int, w: Int) extends Bundle
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{
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val addr = UFix(INPUT, log2Up(d))
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val en = Bool(INPUT)
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val data = Bits(INPUT, w)
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override def clone = new ioWritePort(d, w).asInstanceOf[this.type]
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}
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