133 lines
3.3 KiB
Scala
133 lines
3.3 KiB
Scala
package rocket
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package constants
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import Chisel._
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import scala.math._
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trait ScalarOpConstants {
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val SZ_BR = 3
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val BR_X = Bits("b???", 3)
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val BR_EQ = Bits(0, 3)
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val BR_NE = Bits(1, 3)
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val BR_J = Bits(2, 3)
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val BR_N = Bits(3, 3)
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val BR_LT = Bits(4, 3)
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val BR_GE = Bits(5, 3)
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val BR_LTU = Bits(6, 3)
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val BR_GEU = Bits(7, 3)
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val PC_EX4 = UFix(0, 2)
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val PC_EX = UFix(1, 2)
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val PC_WB = UFix(2, 2)
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val PC_PCR = UFix(3, 2)
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val A2_X = Bits("b???", 3)
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val A2_BTYPE = UFix(0, 3);
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val A2_LTYPE = UFix(1, 3);
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val A2_ITYPE = UFix(2, 3);
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val A2_ZERO = UFix(4, 3);
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val A2_JTYPE = UFix(5, 3);
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val A2_RTYPE = UFix(6, 3);
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val X = Bits("b?", 1)
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val N = Bits(0, 1);
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val Y = Bits(1, 1);
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val WA_X = X
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val WA_RD = N
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val WA_RA = Y
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val WB_X = Bits("b???", 3)
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val WB_PC = UFix(0, 3);
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val WB_ALU = UFix(2, 3);
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val WB_TSC = UFix(4, 3);
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val WB_IRT = UFix(5, 3);
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val SZ_DW = 1
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val DW_X = X
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val DW_32 = N
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val DW_64 = Y
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val DW_XPR = Y
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val RA = UFix(1, 5);
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}
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trait PCRConstants {
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val PCR_X = Bits("b???", 3)
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val PCR_N = Bits(0,3)
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val PCR_F = Bits(1,3) // mfpcr
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val PCR_T = Bits(4,3) // mtpcr
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val PCR_C = Bits(6,3) // clearpcr
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val PCR_S = Bits(7,3) // setpcr
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val PCR_STATUS = UFix( 0, 5);
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val PCR_EPC = UFix( 1, 5);
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val PCR_BADVADDR = UFix( 2, 5);
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val PCR_EVEC = UFix( 3, 5);
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val PCR_COUNT = UFix( 4, 5);
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val PCR_COMPARE = UFix( 5, 5);
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val PCR_CAUSE = UFix( 6, 5);
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val PCR_PTBR = UFix( 7, 5);
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val PCR_SEND_IPI = UFix( 8, 5);
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val PCR_CLR_IPI = UFix( 9, 5);
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val PCR_COREID = UFix(10, 5);
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val PCR_IMPL = UFix(11, 5);
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val PCR_K0 = UFix(12, 5);
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val PCR_K1 = UFix(13, 5);
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val PCR_VECBANK = UFix(18, 5);
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val PCR_VECCFG = UFix(19, 5);
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val PCR_RESET = UFix(29, 5);
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val PCR_TOHOST = UFix(30, 5);
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val PCR_FROMHOST = UFix(31, 5);
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// definition of bits in PCR status reg
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val SR_ET = 0; // enable traps
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val SR_EF = 1; // enable floating point
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val SR_EV = 2; // enable vector unit
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val SR_EC = 3; // enable compressed instruction encoding
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val SR_PS = 4; // mode stack bit
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val SR_S = 5; // user/supervisor mode
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val SR_U64 = 6; // 64 bit user mode
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val SR_S64 = 7; // 64 bit supervisor mode
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val SR_VM = 8 // VM enable
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val SR_IM = 16 // interrupt mask
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val SR_IM_WIDTH = 8
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}
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trait InterruptConstants {
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val CAUSE_INTERRUPT = 32
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val IRQ_IPI = 5
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val IRQ_TIMER = 7
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}
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abstract trait RocketDcacheConstants extends uncore.constants.CacheConstants with uncore.constants.AddressConstants {
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require(OFFSET_BITS == log2Up(uncore.Constants.CACHE_DATA_SIZE_IN_BYTES))
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require(OFFSET_BITS <= uncore.Constants.X_INIT_WRITE_MASK_BITS)
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require(log2Up(OFFSET_BITS) <= uncore.Constants.X_INIT_SUBWORD_ADDR_BITS)
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}
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trait VectorOpConstants {
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val VEC_X = Bits("b??", 2).toUFix
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val VEC_FN_N = UFix(0, 2)
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val VEC_VL = UFix(1, 2)
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val VEC_CFG = UFix(2, 2)
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val VEC_CFGVL = UFix(3, 2)
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val VCMD_I = UFix(0, 3)
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val VCMD_F = UFix(1, 3)
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val VCMD_TX = UFix(2, 3)
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val VCMD_TF = UFix(3, 3)
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val VCMD_MX = UFix(4, 3)
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val VCMD_MF = UFix(5, 3)
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val VCMD_A = UFix(6, 3)
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val VCMD_X = UFix(0, 3)
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val VIMM_VLEN = UFix(0, 1)
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val VIMM_ALU = UFix(1, 1)
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val VIMM_X = UFix(0, 1)
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val VIMM2_RS2 = UFix(0, 1)
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val VIMM2_ALU = UFix(1, 1)
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val VIMM2_X = UFix(0, 1)
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}
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