e0d849fec5
Use the following command in vsim: make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
78 lines
2.3 KiB
Plaintext
78 lines
2.3 KiB
Plaintext
#--------------------------------------------------------------------
|
|
# Sources
|
|
#--------------------------------------------------------------------
|
|
|
|
# Verilog sources
|
|
|
|
sim_vsrcs = \
|
|
$(generated_dir)/$(MODEL).$(CONFIG).v \
|
|
$(generated_dir)/consts.$(CONFIG).vh \
|
|
$(generated_dir)/memdessertMemDessert.$(CONFIG).v \
|
|
$(base_dir)/vsrc/$(TB).v \
|
|
$(base_dir)/vsrc/backup_mem.v \
|
|
|
|
# C sources
|
|
|
|
sim_csrcs = \
|
|
$(base_dir)/csrc/vcs_main.$(TB).cc \
|
|
$(base_dir)/csrc/mm.cc \
|
|
$(base_dir)/csrc/mm_dramsim2.cc \
|
|
|
|
#--------------------------------------------------------------------
|
|
# Build Verilog
|
|
#--------------------------------------------------------------------
|
|
|
|
verilog: $(sim_vsrcs)
|
|
|
|
.PHONY: verilog
|
|
|
|
#--------------------------------------------------------------------
|
|
# Build rules
|
|
#--------------------------------------------------------------------
|
|
|
|
VCS = vcs -full64
|
|
|
|
VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
|
|
+rad +v2k +vcs+lic+wait \
|
|
+vc+list -CC "-I$(VCS_HOME)/include" \
|
|
-CC "-I$(RISCV)/include" \
|
|
-CC "-I$(realpath $(base_dir))/dramsim2" \
|
|
-CC "-std=c++11" \
|
|
-CC "-Wl,-rpath,$(RISCV)/lib" \
|
|
-CC "-include $(consts_header)" \
|
|
-e vcs_main \
|
|
$(RISCV)/lib/libfesvr.so \
|
|
$(sim_dir)/libdramsim.a \
|
|
+incdir+$(generated_dir) \
|
|
+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
|
|
+define+PRINTF_COND=$(TB).verbose \
|
|
+libext+.v \
|
|
|
|
#--------------------------------------------------------------------
|
|
# Build the simulator
|
|
#--------------------------------------------------------------------
|
|
|
|
simv = $(sim_dir)/simv-$(MODEL)-$(CONFIG)
|
|
$(simv) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a $(consts_header)
|
|
cd $(sim_dir) && \
|
|
rm -rf csrc && \
|
|
$(VCS) $(VCS_OPTS) -o $(simv) \
|
|
-debug_pp \
|
|
|
|
simv_debug = $(sim_dir)/simv-$(MODEL)-$(CONFIG)-debug
|
|
$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a $(consts_header)
|
|
cd $(sim_dir) && \
|
|
rm -rf csrc && \
|
|
$(VCS) $(VCS_OPTS) -o $(simv_debug) \
|
|
+define+DEBUG -debug_pp \
|
|
|
|
# +define+MEM_BACKUP_EN \
|
|
|
|
#--------------------------------------------------------------------
|
|
# Run
|
|
#--------------------------------------------------------------------
|
|
|
|
seed = $(shell date +%s)
|
|
exec_simv = $(simv) -q +ntb_random_seed_automatic
|
|
exec_simv_debug = $(simv_debug) -q +ntb_random_seed_automatic
|