01ca3efc2b
* coreplex collapse: peripherals now in coreplex * coreplex: better factoring of TLBusWrapper attachement points * diplomacy: allow monitorless :*= and :=* * rocket: don't connect monitors to tile tim slave ports * rename chip package to system * coreplex: only sbus has a splitter * TLFragmenter: Continuing my spot battles on requires without explanatory strings * pbus: toFixedWidthSingleBeatSlave * tilelink: more verbose requires * use the new system package for regression * sbus: add more explicit FIFO attachment points * delete leftover top-level utils * cleanup ResetVector and RTC
16 lines
427 B
Scala
16 lines
427 B
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.groundtest
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy.LazyModule
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class TestHarness(implicit p: Parameters) extends Module {
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val io = new Bundle { val success = Bool(OUTPUT) }
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val dut = Module(LazyModule(new GroundTestCoreplex).module)
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io.success := dut.success
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dut.connectSimAXIMem()
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}
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