275 lines
11 KiB
Scala
275 lines
11 KiB
Scala
// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package rocket
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import Chisel._
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import Chisel.ImplicitConversions._
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import config._
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import tile.HasCoreParameters
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import util._
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case class BTBParams(
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nEntries: Int = 40,
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nMatchBits: Int = 14,
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nPages: Int = 6,
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nRAS: Int = 2,
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updatesOutOfOrder: Boolean = false)
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trait HasBtbParameters extends HasCoreParameters {
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val btbParams = tileParams.btb.getOrElse(BTBParams(nEntries = 0))
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val matchBits = btbParams.nMatchBits max log2Ceil(p(coreplex.CacheBlockBytes) * tileParams.icache.get.nSets)
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val entries = btbParams.nEntries
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val nRAS = btbParams.nRAS
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val updatesOutOfOrder = btbParams.updatesOutOfOrder
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val nPages = (btbParams.nPages + 1) / 2 * 2 // control logic assumes 2 divides pages
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val opaqueBits = log2Up(entries)
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val nBHT = 1 << log2Up(entries*2)
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}
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abstract class BtbModule(implicit val p: Parameters) extends Module with HasBtbParameters
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abstract class BtbBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasBtbParameters
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class RAS(nras: Int) {
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def push(addr: UInt): Unit = {
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when (count < nras) { count := count + 1 }
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val nextPos = Mux(Bool(isPow2(nras)) || pos < nras-1, pos+1, UInt(0))
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stack(nextPos) := addr
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pos := nextPos
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}
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def peek: UInt = stack(pos)
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def pop(): Unit = when (!isEmpty) {
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count := count - 1
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pos := Mux(Bool(isPow2(nras)) || pos > 0, pos-1, UInt(nras-1))
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}
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def clear(): Unit = count := UInt(0)
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def isEmpty: Bool = count === UInt(0)
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private val count = Reg(UInt(width = log2Up(nras+1)))
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private val pos = Reg(UInt(width = log2Up(nras)))
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private val stack = Reg(Vec(nras, UInt()))
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}
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class BHTResp(implicit p: Parameters) extends BtbBundle()(p) {
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val history = UInt(width = log2Up(nBHT).max(1))
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val value = UInt(width = 2)
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}
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// BHT contains table of 2-bit counters and a global history register.
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// The BHT only predicts and updates when there is a BTB hit.
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// The global history:
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// - updated speculatively in fetch (if there's a BTB hit).
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// - on a mispredict, the history register is reset (again, only if BTB hit).
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// The counter table:
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// - each counter corresponds with the address of the fetch packet ("fetch pc").
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// - updated when a branch resolves (and BTB was a hit for that branch).
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// The updating branch must provide its "fetch pc".
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class BHT(nbht: Int)(implicit val p: Parameters) extends HasCoreParameters {
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val nbhtbits = log2Up(nbht)
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def get(addr: UInt, update: Bool): BHTResp = {
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val res = Wire(new BHTResp)
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val index = addr(nbhtbits+1, log2Up(coreInstBytes)) ^ history
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res.value := table(index)
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res.history := history
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val taken = res.value(0)
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when (update) { history := Cat(taken, history(nbhtbits-1,1)) }
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res
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}
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def update(addr: UInt, d: BHTResp, taken: Bool, mispredict: Bool): Unit = {
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val index = addr(nbhtbits+1, log2Up(coreInstBytes)) ^ d.history
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table(index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken))
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when (mispredict) { history := Cat(taken, d.history(nbhtbits-1,1)) }
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}
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private val table = Mem(nbht, UInt(width = 2))
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val history = Reg(UInt(width = nbhtbits))
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}
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// BTB update occurs during branch resolution (and only on a mispredict).
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// - "pc" is what future fetch PCs will tag match against.
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// - "br_pc" is the PC of the branch instruction.
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class BTBUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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val prediction = Valid(new BTBResp)
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val pc = UInt(width = vaddrBits)
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val target = UInt(width = vaddrBits)
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val taken = Bool()
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val isValid = Bool()
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val isJump = Bool()
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val isReturn = Bool()
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val br_pc = UInt(width = vaddrBits)
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}
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// BHT update occurs during branch resolution on all conditional branches.
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// - "pc" is what future fetch PCs will tag match against.
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class BHTUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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val prediction = Valid(new BTBResp)
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val pc = UInt(width = vaddrBits)
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val taken = Bool()
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val mispredict = Bool()
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}
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class RASUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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val isCall = Bool()
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val isReturn = Bool()
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val returnAddr = UInt(width = vaddrBits)
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val prediction = Valid(new BTBResp)
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}
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// - "bridx" is the low-order PC bits of the predicted branch (after
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// shifting off the lowest log(inst_bytes) bits off).
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// - "mask" provides a mask of valid instructions (instructions are
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// masked off by the predicted taken branch from the BTB).
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class BTBResp(implicit p: Parameters) extends BtbBundle()(p) {
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val taken = Bool()
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val mask = Bits(width = fetchWidth)
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val bridx = Bits(width = log2Up(fetchWidth))
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val target = UInt(width = vaddrBits)
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val entry = UInt(width = opaqueBits)
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val bht = new BHTResp
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}
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class BTBReq(implicit p: Parameters) extends BtbBundle()(p) {
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val addr = UInt(width = vaddrBits)
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}
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// fully-associative branch target buffer
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// Higher-performance processors may cause BTB updates to occur out-of-order,
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// which requires an extra CAM port for updates (to ensure no duplicates get
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// placed in BTB).
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class BTB(implicit p: Parameters) extends BtbModule {
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val io = new Bundle {
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val req = Valid(new BTBReq).flip
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val resp = Valid(new BTBResp)
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val btb_update = Valid(new BTBUpdate).flip
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val bht_update = Valid(new BHTUpdate).flip
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val ras_update = Valid(new RASUpdate).flip
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}
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val idxs = Reg(Vec(entries, UInt(width=matchBits - log2Up(coreInstBytes))))
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val idxPages = Reg(Vec(entries, UInt(width=log2Up(nPages))))
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val tgts = Reg(Vec(entries, UInt(width=matchBits - log2Up(coreInstBytes))))
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val tgtPages = Reg(Vec(entries, UInt(width=log2Up(nPages))))
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val pages = Reg(Vec(nPages, UInt(width=vaddrBits - matchBits)))
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val pageValid = Reg(init = UInt(0, nPages))
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val isValid = Reg(init = UInt(0, entries))
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val isReturn = Reg(UInt(width = entries))
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val isJump = Reg(UInt(width = entries))
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val brIdx = Reg(Vec(entries, UInt(width=log2Up(fetchWidth))))
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private def page(addr: UInt) = addr >> matchBits
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private def pageMatch(addr: UInt) = {
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val p = page(addr)
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pageValid & pages.map(_ === p).asUInt
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}
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private def idxMatch(addr: UInt) = {
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val idx = addr(matchBits-1, log2Up(coreInstBytes))
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idxs.map(_ === idx).asUInt & isValid
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}
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val r_btb_update = Pipe(io.btb_update)
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val update_target = io.req.bits.addr
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val pageHit = pageMatch(io.req.bits.addr)
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val idxHit = idxMatch(io.req.bits.addr)
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val updatePageHit = pageMatch(r_btb_update.bits.pc)
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val (updateHit, updateHitAddr) =
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if (updatesOutOfOrder) {
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val updateHits = (pageHit << 1)(Mux1H(idxMatch(r_btb_update.bits.pc), idxPages))
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(updateHits.orR, OHToUInt(updateHits))
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} else (r_btb_update.bits.prediction.valid, r_btb_update.bits.prediction.bits.entry)
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val useUpdatePageHit = updatePageHit.orR
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val usePageHit = pageHit.orR
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val doIdxPageRepl = !useUpdatePageHit
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val nextPageRepl = Reg(UInt(width = log2Ceil(nPages)))
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val idxPageRepl = Cat(pageHit(nPages-2,0), pageHit(nPages-1)) | Mux(usePageHit, UInt(0), UIntToOH(nextPageRepl))
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val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
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val idxPageUpdate = OHToUInt(idxPageUpdateOH)
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val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
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val samePage = page(r_btb_update.bits.pc) === page(update_target)
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val doTgtPageRepl = !samePage && !usePageHit
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val tgtPageRepl = Mux(samePage, idxPageUpdateOH, Cat(idxPageUpdateOH(nPages-2,0), idxPageUpdateOH(nPages-1)))
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val tgtPageUpdate = OHToUInt(pageHit | Mux(usePageHit, UInt(0), tgtPageRepl))
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val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0))
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when (r_btb_update.valid && (doIdxPageRepl || doTgtPageRepl)) {
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val both = doIdxPageRepl && doTgtPageRepl
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val next = nextPageRepl + Mux[UInt](both, 2, 1)
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nextPageRepl := Mux(next >= nPages, next(0), next)
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}
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when (r_btb_update.valid) {
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val nextRepl = Counter(r_btb_update.valid && !updateHit, entries)._1
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val waddr = Mux(updateHit, updateHitAddr, nextRepl)
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val mask = UIntToOH(waddr)
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idxs(waddr) := r_btb_update.bits.pc(matchBits-1, log2Up(coreInstBytes))
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tgts(waddr) := update_target(matchBits-1, log2Up(coreInstBytes))
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idxPages(waddr) := idxPageUpdate +& 1 // the +1 corresponds to the <<1 on io.resp.valid
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tgtPages(waddr) := tgtPageUpdate
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isValid := Mux(r_btb_update.bits.isValid, isValid | mask, isValid & ~mask)
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isReturn := Mux(r_btb_update.bits.isReturn, isReturn | mask, isReturn & ~mask)
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isJump := Mux(r_btb_update.bits.isJump, isJump | mask, isJump & ~mask)
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if (fetchWidth > 1)
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brIdx(waddr) := r_btb_update.bits.br_pc >> log2Up(coreInstBytes)
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require(nPages % 2 == 0)
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val idxWritesEven = !idxPageUpdate(0)
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def writeBank(i: Int, mod: Int, en: UInt, data: UInt) =
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for (i <- i until nPages by mod)
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when (en(i)) { pages(i) := data }
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writeBank(0, 2, Mux(idxWritesEven, idxPageReplEn, tgtPageReplEn),
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Mux(idxWritesEven, page(r_btb_update.bits.pc), page(update_target)))
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writeBank(1, 2, Mux(idxWritesEven, tgtPageReplEn, idxPageReplEn),
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Mux(idxWritesEven, page(update_target), page(r_btb_update.bits.pc)))
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pageValid := pageValid | tgtPageReplEn | idxPageReplEn
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}
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io.resp.valid := (pageHit << 1)(Mux1H(idxHit, idxPages))
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io.resp.bits.taken := true
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io.resp.bits.target := Cat(pages(Mux1H(idxHit, tgtPages)), Mux1H(idxHit, tgts) << log2Up(coreInstBytes))
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io.resp.bits.entry := OHToUInt(idxHit)
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io.resp.bits.bridx := (if (fetchWidth > 1) Mux1H(idxHit, brIdx) else UInt(0))
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io.resp.bits.mask := Cat((UInt(1) << ~Mux(io.resp.bits.taken, ~io.resp.bits.bridx, UInt(0)))-1, UInt(1))
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// if multiple entries for same PC land in BTB, zap them
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when (PopCountAtLeast(idxHit, 2)) {
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isValid := isValid & ~idxHit
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}
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if (nBHT > 0) {
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val bht = new BHT(nBHT)
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val isBranch = !(idxHit & isJump).orR
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val res = bht.get(io.req.bits.addr, io.req.valid && io.resp.valid && isBranch)
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val update_btb_hit = io.bht_update.bits.prediction.valid
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when (io.bht_update.valid && update_btb_hit) {
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bht.update(io.bht_update.bits.pc, io.bht_update.bits.prediction.bits.bht, io.bht_update.bits.taken, io.bht_update.bits.mispredict)
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}
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when (!res.value(0) && isBranch) { io.resp.bits.taken := false }
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io.resp.bits.bht := res
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}
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if (nRAS > 0) {
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val ras = new RAS(nRAS)
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val doPeek = (idxHit & isReturn).orR
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when (!ras.isEmpty && doPeek) {
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io.resp.bits.target := ras.peek
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}
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when (io.ras_update.valid) {
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when (io.ras_update.bits.isCall) {
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ras.push(io.ras_update.bits.returnAddr)
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when (doPeek) {
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io.resp.bits.target := io.ras_update.bits.returnAddr
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}
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}.elsewhen (io.ras_update.bits.isReturn && io.ras_update.bits.prediction.valid) {
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ras.pop()
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}
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}
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}
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}
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