Andrew Waterman 5a5b78b15e Improve L2 TLB coding style

2017-07-26 02:22:43 -07:00

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amba

Combine Coreplex and System Module Hierarchies (#875)

2017-07-23 08:31:04 -07:00

config

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

coreplex

coreplex: better names for RocketTiles in Verilog (#890)

2017-07-25 16:35:31 -07:00

devices

Combine Coreplex and System Module Hierarchies (#875)

2017-07-23 08:31:04 -07:00

diplomacy

Combine Coreplex and System Module Hierarchies (#875)

2017-07-23 08:31:04 -07:00

groundtest

chiplink: adjust bus view to include the splitter (#886)

2017-07-24 21:41:17 -07:00

jtag

Use chisel3 Clock() method.

2017-07-07 14:16:39 -07:00

regmapper

add cloneType to RegisterWriteIO and RegisterReadIO (#874)

2017-07-18 18:52:31 -07:00

rocket

Improve L2 TLB coding style

2017-07-26 02:22:43 -07:00

system

Mix in trait to connect global_reset_vector

2017-07-25 15:19:16 -07:00

tile

Perform some control-flow transfers within the Frontend

2017-07-25 15:19:16 -07:00

tilelink

tilelink: fix Fragmenter source re-use bug (#888)

2017-07-25 16:23:55 -07:00

unittest

Combine Coreplex and System Module Hierarchies (#875)

2017-07-23 08:31:04 -07:00

util

Combine Coreplex and System Module Hierarchies (#875)

2017-07-23 08:31:04 -07:00