Palmer Dabbelt a073c37e36 The FPGA doesn't have an HTIF clock divider ...

We used to just be writing the SCR anyway, but now that the SCR maps are
automatically defined VCS will detect the missing SCR and bail out when
compiling test harness code.  This patch just doesn't write the HTIF SCR when
there isn't one.

2016-02-22 16:15:07 -08:00

..

comlog.cc

cleaner/faster comlog without linear search

2015-09-15 17:19:29 -07:00

emulator.cc

add option to print cycle count regardless of exit status

2015-12-04 12:04:13 -08:00

float_fix.cc

remove bugs from float_fix

2015-09-23 16:11:47 -07:00

htif_emulator.h

The FPGA doesn't have an HTIF clock divider

2016-02-22 16:15:07 -08:00

mm_dramsim2.cc

Get rid of MemIO in Top and replace with AXI throughout

2015-11-05 10:48:32 -08:00

mm_dramsim2.h

Get rid of MemIO in Top and replace with AXI throughout

2015-11-05 10:48:32 -08:00

mm.cc

use definitions in consts header whenever possible

2015-11-05 10:48:32 -08:00

mm.h

use definitions in consts header whenever possible

2015-11-05 10:48:32 -08:00

vcs_main.rocketTestHarness.cc

Allow the number of memory channels to be picked at runtime

2016-02-17 15:23:30 -08:00

vcs_main.ZscaleTestHarness.cc

Fix zscale testing

2015-12-01 17:31:48 -08:00