49 lines
1.4 KiB
Scala
49 lines
1.4 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.util
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import Chisel._
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import chisel3.experimental.{withClockAndReset}
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/** Reset: asynchronous assert,
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* synchronous de-assert
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*
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*/
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class ResetCatchAndSync (sync: Int = 3) extends Module {
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override def desiredName = s"ResetCatchAndSync_d${sync}"
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val io = new Bundle {
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val sync_reset = Bool(OUTPUT)
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val psd = new PSDTestMode().asInput
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}
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io.sync_reset := Mux(io.psd.test_mode, io.psd.test_mode_reset,
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~AsyncResetSynchronizerShiftReg(Bool(true), sync))
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}
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object ResetCatchAndSync {
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def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None,
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psd: Option[PSDTestMode] = None): Bool = {
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withClockAndReset(clk, rst) {
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val catcher = Module (new ResetCatchAndSync(sync))
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if (name.isDefined) {catcher.suggestName(name.get)}
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catcher.io.psd <> psd.getOrElse(Wire(new PSDTestMode()).fromBits(UInt(0)))
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catcher.io.sync_reset
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}
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}
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def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
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def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name))
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def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd: PSDTestMode): Bool =
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apply(clk, rst, sync, Some(name), Some(psd))
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def apply(clk: Clock, rst: Bool, name: String, psd: PSDTestMode): Bool =
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apply(clk, rst, name = Some(name), psd = Some(psd))
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}
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