54 lines
1.7 KiB
Scala
54 lines
1.7 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package freechips.rocketchip.groundtest
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.rocket.{DCache, RocketCoreParams}
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import freechips.rocketchip.tile._
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import freechips.rocketchip.tilelink._
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import scala.collection.mutable.ListBuffer
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trait GroundTestTileParams extends TileParams {
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val memStart: BigInt
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val maxRequests: Int
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val numGens: Int
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def build(i: Int, p: Parameters): GroundTestTile
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val icache = None
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val btb = None
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val rocc = Nil
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val core = RocketCoreParams(nPMPs = 0) //TODO remove this
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val cached = if(dcache.isDefined) 1 else 0
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val dataScratchpadBytes = 0
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}
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case object GroundTestTilesKey extends Field[Seq[GroundTestTileParams]]
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abstract class GroundTestTile(params: GroundTestTileParams)
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(implicit p: Parameters)
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extends BaseTile(params, crossing = SynchronousCrossing())(p) {
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val intInwardNode: IntInwardNode = IntIdentityNode()
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val intOutwardNode: IntOutwardNode = IntIdentityNode()
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val slaveNode: TLInwardNode = TLIdentityNode()
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val dcacheOpt = params.dcache.map { dc => LazyModule(new DCache(0)) }
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override lazy val module = new GroundTestTileModuleImp(this)
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}
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class GroundTestTileModuleImp(outer: GroundTestTile) extends BaseTileModuleImp(outer) {
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val status = IO(new GroundTestStatus)
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val halt_and_catch_fire = None
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outer.dcacheOpt foreach { dcache =>
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val ptw = Module(new DummyPTW(1))
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ptw.io.requestors.head <> dcache.module.io.ptw
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}
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}
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