300 lines
8.9 KiB
Scala
300 lines
8.9 KiB
Scala
// See LICENSE for license details.
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package rocket
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import Chisel._
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import uncore._
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import Util._
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import cde.{Parameters, Field}
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case object RoccMaxTaggedMemXacts extends Field[Int]
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case object RoccNMemChannels extends Field[Int]
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case object RoccNPTWPorts extends Field[Int]
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case object RoccNCSRs extends Field[Int]
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class RoCCCSRs(implicit p: Parameters) extends CoreBundle()(p) {
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val rdata = Vec(nRoccCsrs, UInt(INPUT, xLen))
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val waddr = UInt(OUTPUT, CSR.ADDRSZ)
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val wdata = UInt(OUTPUT, xLen)
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val wen = Bool(OUTPUT)
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}
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class RoCCInstruction extends Bundle
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{
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val funct = Bits(width = 7)
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val rs2 = Bits(width = 5)
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val rs1 = Bits(width = 5)
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val xd = Bool()
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val xs1 = Bool()
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val xs2 = Bool()
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val rd = Bits(width = 5)
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val opcode = Bits(width = 7)
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}
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class RoCCCommand(implicit p: Parameters) extends CoreBundle()(p) {
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val inst = new RoCCInstruction
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val rs1 = Bits(width = xLen)
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val rs2 = Bits(width = xLen)
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}
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class RoCCResponse(implicit p: Parameters) extends CoreBundle()(p) {
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val rd = Bits(width = 5)
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val data = Bits(width = xLen)
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}
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class RoCCInterface(implicit p: Parameters) extends CoreBundle()(p) {
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val cmd = Decoupled(new RoCCCommand).flip
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val resp = Decoupled(new RoCCResponse)
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val mem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" }))
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val busy = Bool(OUTPUT)
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val status = new MStatus().asInput
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val interrupt = Bool(OUTPUT)
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// These should be handled differently, eventually
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val autl = new ClientUncachedTileLinkIO
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val utl = Vec(p(RoccNMemChannels), new ClientUncachedTileLinkIO)
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val ptw = Vec(p(RoccNPTWPorts), new TLBPTWIO)
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val fpu_req = Decoupled(new FPInput)
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val fpu_resp = Decoupled(new FPResult).flip
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val exception = Bool(INPUT)
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val csr = (new RoCCCSRs).flip
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val host_id = UInt(INPUT, log2Up(nCores))
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override def cloneType = new RoCCInterface().asInstanceOf[this.type]
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}
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abstract class RoCC(implicit p: Parameters) extends CoreModule()(p) {
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val io = new RoCCInterface
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io.mem.req.bits.phys := Bool(true) // don't perform address translation
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}
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class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) {
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val regfile = Mem(n, UInt(width = xLen))
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val busy = Reg(init = Vec.fill(n){Bool(false)})
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val cmd = Queue(io.cmd)
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val funct = cmd.bits.inst.funct
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val addr = cmd.bits.rs2(log2Up(n)-1,0)
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val doWrite = funct === UInt(0)
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val doRead = funct === UInt(1)
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val doLoad = funct === UInt(2)
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val doAccum = funct === UInt(3)
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val memRespTag = io.mem.resp.bits.tag(log2Up(n)-1,0)
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// datapath
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val addend = cmd.bits.rs1
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val accum = regfile(addr)
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val wdata = Mux(doWrite, addend, accum + addend)
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when (cmd.fire() && (doWrite || doAccum)) {
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regfile(addr) := wdata
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}
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when (io.mem.resp.valid) {
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regfile(memRespTag) := io.mem.resp.bits.data
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}
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// control
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when (io.mem.req.fire()) {
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busy(addr) := Bool(true)
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}
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when (io.mem.resp.valid) {
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busy(memRespTag) := Bool(false)
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}
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val doResp = cmd.bits.inst.xd
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val stallReg = busy(addr)
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val stallLoad = doLoad && !io.mem.req.ready
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val stallResp = doResp && !io.resp.ready
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cmd.ready := !stallReg && !stallLoad && !stallResp
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// command resolved if no stalls AND not issuing a load that will need a request
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// PROC RESPONSE INTERFACE
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io.resp.valid := cmd.valid && doResp && !stallReg && !stallLoad
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// valid response if valid command, need a response, and no stalls
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io.resp.bits.rd := cmd.bits.inst.rd
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// Must respond with the appropriate tag or undefined behavior
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io.resp.bits.data := accum
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// Semantics is to always send out prior accumulator register value
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io.busy := cmd.valid || busy.reduce(_||_)
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// Be busy when have pending memory requests or committed possibility of pending requests
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io.interrupt := Bool(false)
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// Set this true to trigger an interrupt on the processor (please refer to supervisor documentation)
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// MEMORY REQUEST INTERFACE
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io.mem.req.valid := cmd.valid && doLoad && !stallReg && !stallResp
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io.mem.req.bits.addr := addend
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io.mem.req.bits.tag := addr
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io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores)
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io.mem.req.bits.typ := MT_D // D = 8 bytes, W = 4, H = 2, B = 1
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io.mem.req.bits.data := Bits(0) // we're not performing any stores...
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io.mem.invalidate_lr := false
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io.autl.acquire.valid := false
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io.autl.grant.ready := false
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}
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class TranslatorExample(implicit p: Parameters) extends RoCC()(p) {
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val req_addr = Reg(UInt(width = coreMaxAddrBits))
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val req_rd = Reg(io.resp.bits.rd)
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val req_offset = req_addr(pgIdxBits - 1, 0)
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val req_vpn = req_addr(coreMaxAddrBits - 1, pgIdxBits)
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val pte = Reg(new PTE)
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val s_idle :: s_ptw_req :: s_ptw_resp :: s_resp :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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io.cmd.ready := (state === s_idle)
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when (io.cmd.fire()) {
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req_rd := io.cmd.bits.inst.rd
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req_addr := io.cmd.bits.rs1
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state := s_ptw_req
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}
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private val ptw = io.ptw(0)
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when (ptw.req.fire()) { state := s_ptw_resp }
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when (state === s_ptw_resp && ptw.resp.valid) {
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pte := ptw.resp.bits.pte
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state := s_resp
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}
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when (io.resp.fire()) { state := s_idle }
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ptw.req.valid := (state === s_ptw_req)
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ptw.req.bits.addr := req_vpn
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ptw.req.bits.store := Bool(false)
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ptw.req.bits.fetch := Bool(false)
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io.resp.valid := (state === s_resp)
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io.resp.bits.rd := req_rd
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io.resp.bits.data := Mux(pte.leaf(), Cat(pte.ppn, req_offset), ~UInt(0, xLen))
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io.busy := (state =/= s_idle)
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io.interrupt := Bool(false)
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io.mem.req.valid := Bool(false)
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io.autl.acquire.valid := Bool(false)
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io.autl.grant.ready := Bool(false)
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}
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class CharacterCountExample(implicit p: Parameters) extends RoCC()(p)
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with HasTileLinkParameters {
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private val blockOffset = tlBeatAddrBits + tlByteAddrBits
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val needle = Reg(UInt(width = 8))
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val addr = Reg(UInt(width = coreMaxAddrBits))
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val count = Reg(UInt(width = xLen))
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val resp_rd = Reg(io.resp.bits.rd)
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val addr_block = addr(coreMaxAddrBits - 1, blockOffset)
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val offset = addr(blockOffset - 1, 0)
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val next_addr = (addr_block + UInt(1)) << UInt(blockOffset)
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val s_idle :: s_acq :: s_gnt :: s_check :: s_resp :: Nil = Enum(Bits(), 5)
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val state = Reg(init = s_idle)
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val gnt = io.autl.grant.bits
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val recv_data = Reg(UInt(width = tlDataBits))
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val recv_beat = Reg(UInt(width = tlBeatAddrBits))
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val data_bytes = Vec.tabulate(tlDataBytes) { i => recv_data(8 * (i + 1) - 1, 8 * i) }
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val zero_match = data_bytes.map(_ === UInt(0))
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val needle_match = data_bytes.map(_ === needle)
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val first_zero = PriorityEncoder(zero_match)
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val chars_found = PopCount(needle_match.zipWithIndex.map {
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case (matches, i) =>
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val idx = Cat(recv_beat, UInt(i, tlByteAddrBits))
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matches && idx >= offset && UInt(i) <= first_zero
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})
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val zero_found = zero_match.reduce(_ || _)
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val finished = Reg(Bool())
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io.cmd.ready := (state === s_idle)
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io.resp.valid := (state === s_resp)
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io.resp.bits.rd := resp_rd
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io.resp.bits.data := count
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io.autl.acquire.valid := (state === s_acq)
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io.autl.acquire.bits := GetBlock(addr_block = addr_block)
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io.autl.grant.ready := (state === s_gnt)
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when (io.cmd.fire()) {
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addr := io.cmd.bits.rs1
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needle := io.cmd.bits.rs2
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resp_rd := io.cmd.bits.inst.rd
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count := UInt(0)
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finished := Bool(false)
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state := s_acq
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}
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when (io.autl.acquire.fire()) { state := s_gnt }
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when (io.autl.grant.fire()) {
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recv_beat := gnt.addr_beat
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recv_data := gnt.data
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state := s_check
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}
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when (state === s_check) {
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when (!finished) {
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count := count + chars_found
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}
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when (zero_found) { finished := Bool(true) }
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when (recv_beat === UInt(tlDataBeats - 1)) {
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addr := next_addr
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state := Mux(zero_found || finished, s_resp, s_acq)
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} .otherwise {
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state := s_gnt
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}
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}
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when (io.resp.fire()) { state := s_idle }
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io.busy := (state =/= s_idle)
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io.interrupt := Bool(false)
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io.mem.req.valid := Bool(false)
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}
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class OpcodeSet(val opcodes: Seq[UInt]) {
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def |(set: OpcodeSet) =
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new OpcodeSet(this.opcodes ++ set.opcodes)
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def matches(oc: UInt) = opcodes.map(_ === oc).reduce(_ || _)
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}
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object OpcodeSet {
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val custom0 = new OpcodeSet(Seq(Bits("b0001011")))
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val custom1 = new OpcodeSet(Seq(Bits("b0101011")))
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val custom2 = new OpcodeSet(Seq(Bits("b1011011")))
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val custom3 = new OpcodeSet(Seq(Bits("b1111011")))
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val all = custom0 | custom1 | custom2 | custom3
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}
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class RoccCommandRouter(opcodes: Seq[OpcodeSet])(implicit p: Parameters)
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extends CoreModule()(p) {
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val io = new Bundle {
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val in = Decoupled(new RoCCCommand).flip
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val out = Vec(opcodes.size, Decoupled(new RoCCCommand))
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val busy = Bool(OUTPUT)
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}
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val cmd = Queue(io.in)
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val cmdReadys = io.out.zip(opcodes).map { case (out, opcode) =>
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val me = opcode.matches(cmd.bits.inst.opcode)
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out.valid := cmd.valid && me
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out.bits := cmd.bits
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out.ready && me
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}
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cmd.ready := cmdReadys.reduce(_ || _)
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io.busy := cmd.valid
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assert(PopCount(cmdReadys) <= UInt(1),
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"Custom opcode matched for more than one accelerator")
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}
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