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rocket-chip/fsim
Palmer Dabbelt db9de94588 Generate and use SCR address header files
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
2016-02-17 15:23:18 -08:00
..
.gitignore update for rocket-chip release 2014-08-31 20:26:55 -07:00
fpga_mem_gen Fix fpga_mem_gen for Python 2 and 3 Environments 2015-06-25 11:03:33 -07:00
Makefile Allow the regression Makefile to clean all targets 2016-01-31 23:06:59 -08:00
Makefrag Generate and use SCR address header files 2016-02-17 15:23:18 -08:00