d3ccec1044
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API. * Additional tests. * New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit * Updated TileLink protocol, NASTI protocol SHIMs. * Lays groundwork for multiple top-level memory channels, superscalar fetch. * Bump all submodules.
32 lines
843 B
Bash
Executable File
32 lines
843 B
Bash
Executable File
#! /bin/bash
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#
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# See LICENSE for license details.
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# Script to setup submodules, build rocket-chip, and run asm tests, and optionally run torture
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echo "Starting Rocket-chip regression test"
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if [ $# -lt 1 ]
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then
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echo "Usage: ./regression.sh config [torture_config] [torture_output_dir]"
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exit
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fi
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git submodule update --init --recursive riscv-tools
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export RISCV="$(pwd)/install"; export PATH=$PATH:$RISCV/bin
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cd riscv-tools; ./build.sh; cd ..
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git submodule update --init
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git submodule status --recursive
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cd emulator; make CONFIG=$1 run-asm-tests; cd ..
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if [ $# -ge 2 ]
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then
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git clone git@github.com:ucb-bar/riscv-torture.git
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cd riscv-torture; git submodule update --init;
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if [ $# -eq 3 ]
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then
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make cnight RTL_CONFIG=$1 OPTIONS="-C $2 -p $3 -m 30 -t 10"
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else
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make cnight RTL_CONFIG=$1 OPTIONS="-C $2 -m 30 -t 10"
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fi
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fi
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