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riscv/rocket-chip
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4f58aab26f1dc93e89b5afab66bca0951c320d36
rocket-chip/src/main/scala
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Andrew Waterman 026fa14bf8 Rename trace.addr -> iaddr
2017-09-20 14:32:41 -07:00
..
amba
adapters: support bulk connections
2017-09-07 16:03:35 -07:00
config
config: use Field defaults over Config defaults
2017-09-13 11:25:42 -07:00
coreplex
Integrate L1 BusErrorUnit
2017-09-20 00:05:07 -07:00
devices
Merge remote-tracking branch 'origin/test_mode_reset' into test_mode_reset
2017-09-17 13:51:46 -07:00
diplomacy
Scan AddressDecoder bits left to right
2017-09-19 17:47:24 -07:00
groundtest
Add instruction-trace port
2017-09-19 22:59:57 -07:00
jtag
Jtagresettobool - add explicit toBool cast now required on reset. (#984)
2017-09-06 09:49:47 -07:00
regmapper
add cloneType to RegisterWriteIO and RegisterReadIO (#874)
2017-07-18 18:52:31 -07:00
rocket
Rename trace.addr -> iaddr
2017-09-20 14:32:41 -07:00
system
config: use Field defaults over Config defaults
2017-09-13 11:25:42 -07:00
tile
Merge pull request #994 from freechipsproject/beu
2017-09-20 12:17:08 -07:00
tilelink
Add cover property API that can be refined through Config PropertyLibrary (#998)
2017-09-19 19:26:54 -07:00
unittest
Combine Coreplex and System Module Hierarchies (#875)
2017-07-23 08:31:04 -07:00
util
Support SynchronizerShiftReg(sync = 0)
2017-09-20 00:05:07 -07:00
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