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riscv
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rocket-chip
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4f06a5ff6b
rocket-chip
/
vsim
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Howard Mao
c831a0a4e5
use scala firrtl instead of stanza firrtl
2016-03-30 19:35:25 -07:00
..
.gitignore
update for rocket-chip release
2014-08-31 20:26:55 -07:00
Makefile
Add CHISEL_VERSION make argument
2016-03-24 12:00:13 -07:00
Makefrag
Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter"
2016-03-30 19:06:32 -07:00
Makefrag-verilog
use scala firrtl instead of stanza firrtl
2016-03-30 19:35:25 -07:00
vlsi_mem_gen
Massive update containing several months of changes from the now-defunct private chip repo.
2015-07-02 14:43:30 -07:00