75 lines
3.8 KiB
Scala
75 lines
3.8 KiB
Scala
import sbt._
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import Keys._
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//val extracted: Extracted = Project.extract(state)
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//import extracted._
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object BuildSettings extends Build {
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val buildOrganization = "berkeley"
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val buildVersion = "1.1"
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val buildScalaVersion = "2.9.2"
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val chiselDebug = SettingKey[Boolean]("chisel-debug", "generated backend sources with debug signals")
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val chiselArgsDebug = SettingKey[Seq[String]]("chisel-args-debug", "additional chisel args for debug backend signals")
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val chiselArgsC = SettingKey[Seq[String]]("chisel-args-c", "default chisel args for c backend")
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val chiselArgsVlsi = SettingKey[Seq[String]]("chisel-args-vlsi", "default chisel args for vlsi backend")
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val chiselArgsFpga = SettingKey[Seq[String]]("chisel-args-fpga", "default chisel args for fpga backend")
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val buildSettings = Defaults.defaultSettings ++ Seq (
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//unmanagedBase <<= baseDirectory { base => base / ".." / custom_lib" },
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organization := buildOrganization,
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version := buildVersion,
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scalaVersion := buildScalaVersion,
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chiselDebug := false,
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chiselArgsDebug := Seq("--debug","--vcd"),
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chiselArgsC := "--targetDir ../emulator/generated-src --backend c".split(" "),
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chiselArgsFpga := "--targetDir ../fpga/generated-src --backend fpga".split(" "),
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chiselArgsVlsi := "--targetDir ../vlsi/generated-src --backend v".split(" ")
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)
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lazy val chisel = Project("chisel", file("chisel"), settings = buildSettings)
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lazy val hardfloat = Project("hardfloat", file("hardfloat"), settings = buildSettings) dependsOn(chisel)
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lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(hardfloat,chisel)
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lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(chisel)
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lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore,hwacha,hardfloat,chisel)
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lazy val referencechip = Project("referencechip", file("referencechip"), settings = buildSettings ++ chipSettings) dependsOn(chisel,rocket)
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val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code")
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val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command")
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val chipSettings = Seq(
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elaborateTask <<= inputTask { (argTask: TaskKey[Seq[String]]) =>
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(argTask, fullClasspath in Runtime, thisProject, chiselDebug, chiselArgsDebug) map {
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(args: Seq[String], cp: Classpath, pr: ResolvedProject, debug: Boolean, debugArgs: Seq[String]) => {
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val numArgs = 1
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require(args.length >= numArgs, "syntax: elaborate <component> [chisel args]")
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val projectName = pr.id
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val packageName = projectName //TODO: valid convention?
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val componentName = args(0)
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val optionalArgs = if(debug) debugArgs else Nil
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val classLoader = new java.net.URLClassLoader(cp.map(_.data.toURL).toArray, cp.getClass.getClassLoader)
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val chiselMainClass = classLoader.loadClass("Chisel.chiselMain$")
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val chiselMainObject = chiselMainClass.getDeclaredFields.head.get(null)
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val chiselMain = chiselMainClass.getMethod("run", classOf[Array[String]], classOf[Function0[_]])
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val chiselArgs = args.drop(numArgs) ++ optionalArgs
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val component = classLoader.loadClass(packageName+"."+componentName)
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val generator = () => component.newInstance()
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chiselMain.invoke(chiselMainObject, Array(chiselArgs.toArray, generator):_*)
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}
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}
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},
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makeTask <<= inputTask { (argTask: TaskKey[Seq[String]]) =>
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(argTask) map {
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(args: Seq[String]) => {
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require(args.length >= 2, "syntax: <dir> <target>")
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val makeDir = args(0)
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val target = args(1)
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val jobs = java.lang.Runtime.getRuntime.availableProcessors
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val make = "make -C" + makeDir + " -j" + jobs + " " + target
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make!
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}
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}
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}
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)
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}
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