926efd0cab
We're building a chip with 8 memory channels. Since this will require a complicated test setup we want to also be able to bring up the chip with fewer memory channels. This commit adds a SCR that controls the number of active memory channels on a chip. Toggling this SCR will scramble memory and drop Nasti messages, so it's only possible to change while the chip is booting. By default this just adds a 1-bit SCR, which essentially no extra logic. When multiple memory channel configurations are enabled at elaboration time, a NastiMemoryInterconnect is generated for each channel configuration. The number of outstanding misses is increased to coorespond to the maximum number of banks per memory channel (added as a parameter), which I believe is necessary to avoid deadlock in the memory system. A configuration is added that supports 8 memory channels but has only 1 enabled by default. |
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| .. | ||
| comlog.cc | ||
| emulator.cc | ||
| float_fix.cc | ||
| htif_emulator.h | ||
| mm_dramsim2.cc | ||
| mm_dramsim2.h | ||
| mm.cc | ||
| mm.h | ||
| vcs_main.rocketTestHarness.cc | ||
| vcs_main.ZscaleTestHarness.cc | ||