47 lines
1.5 KiB
Scala
47 lines
1.5 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import scala.math.{min,max}
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// Moves the AddressSets of slave devices around
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// Combine with TLFilter to remove slaves or reduce their size
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class TLMap(fn: AddressSet => BigInt)(implicit p: Parameters) extends LazyModule
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{
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val node = TLAdapterNode(
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clientFn = { cp => cp },
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managerFn = { mp =>
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mp.copy(managers = mp.managers.map(m =>
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m.copy(address = m.address.map(a =>
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AddressSet(fn(a), a.mask)))))})
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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out <> in
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val convert = edgeIn.manager.managers.flatMap(_.address) zip edgeOut.manager.managers.flatMap(_.address)
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def forward(x: UInt) =
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convert.map { case (i, o) => Mux(i.contains(x), UInt(o.base) | (x & UInt(o.mask)), UInt(0)) }.reduce(_ | _)
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def backward(x: UInt) =
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convert.map { case (i, o) => Mux(o.contains(x), UInt(i.base) | (x & UInt(i.mask)), UInt(0)) }.reduce(_ | _)
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out.a.bits.address := forward(in.a.bits.address)
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if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
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out.c.bits.address := forward(in.c.bits.address)
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in.b.bits.address := backward(out.b.bits.address)
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}
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}
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}
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}
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object TLMap
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{
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def apply(fn: AddressSet => BigInt)(implicit p: Parameters): TLNode =
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{
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val map = LazyModule(new TLMap(fn))
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map.node
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}
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}
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