38 lines
898 B
Scala
38 lines
898 B
Scala
// See LICENSE.SiFive for license details.
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package rocketchip
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import Chisel._
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import coreplex.RocketPlex
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import diplomacy.LazyModule
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trait RocketPlexMaster extends HasTopLevelNetworks {
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val module: RocketPlexMasterModule
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val coreplex = LazyModule(new RocketPlex)
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coreplex.l2in :=* fsb.node
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bsb.node :*= coreplex.l2out
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socBus.node := coreplex.mmio
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coreplex.mmioInt := intBus.intnode
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require (mem.size == coreplex.mem.size)
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(mem zip coreplex.mem) foreach { case (xbar, channel) => xbar.node :=* channel }
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}
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trait RocketPlexMasterBundle extends HasTopLevelNetworksBundle {
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val outer: RocketPlexMaster
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}
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trait RocketPlexMasterModule extends HasTopLevelNetworksModule {
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val outer: RocketPlexMaster
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val io: RocketPlexMasterBundle
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val clock: Clock
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val reset: Bool
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outer.coreplex.module.io.tcrs.foreach { case tcr =>
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tcr.clock := clock
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tcr.reset := reset
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}
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}
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