72 lines
2.5 KiB
Scala
72 lines
2.5 KiB
Scala
// See LICENSE.SiFive for license details.
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package rocketchip
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import Chisel._
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import config._
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import junctions._
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import diplomacy._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.devices._
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import util._
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import rocket._
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/** BareTop is the root class for creating a top-level RTL module */
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abstract class BareTop(implicit p: Parameters) extends LazyModule {
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ElaborationArtefacts.add("graphml", graphML)
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}
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abstract class BareTopBundle[+L <: BareTop](_outer: L) extends GenericParameterizedBundle(_outer) {
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val outer = _outer
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implicit val p = outer.p
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}
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abstract class BareTopModule[+L <: BareTop, +B <: BareTopBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
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val outer = _outer
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val io = _io ()
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}
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/** HasTopLevelNetworks provides buses that will serve as attachment points,
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* for use in sub-traits that connect individual agents or external ports.
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*/
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trait HasTopLevelNetworks extends HasPeripheryParameters {
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val module: HasTopLevelNetworksModule
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val socBus = LazyModule(new TLXbar) // Wide or unordered-access slave devices (TL-UH)
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val peripheryBus = LazyModule(new TLXbar) // Narrow and ordered-access slave devices (TL-UL)
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val intBus = LazyModule(new IntXbar) // Device and global external interrupts
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val fsb = LazyModule(new TLBuffer(BufferParams.none)) // Master devices talking to the frontside of the L2
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val bsb = LazyModule(new TLBuffer(BufferParams.none)) // Slave devices talking to the backside of the L2
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val mem = Seq.fill(nMemoryChannels) { LazyModule(new TLXbar) } // Ports out to DRAM
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// The peripheryBus hangs off of socBus;
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// here we convert TL-UH -> TL-UL
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peripheryBus.node :=
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TLBuffer()(
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TLWidthWidget(socBusConfig.beatBytes)(
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TLAtomicAutomata(arithmetic = peripheryBusArithmetic)(
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socBus.node)))
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}
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trait HasTopLevelNetworksBundle extends HasPeripheryParameters {
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val outer: HasTopLevelNetworks
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}
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trait HasTopLevelNetworksModule extends HasPeripheryParameters {
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val outer: HasTopLevelNetworks
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val io: HasTopLevelNetworksBundle
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}
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/** Base Top class with no peripheral devices or ports added */
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class BaseTop(implicit p: Parameters) extends BareTop
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with HasTopLevelNetworks {
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override lazy val module = new BaseTopModule(this, () => new BaseTopBundle(this))
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}
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class BaseTopBundle[+L <: BaseTop](_outer: L) extends BareTopBundle(_outer)
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with HasTopLevelNetworksBundle
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class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io)
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with HasTopLevelNetworksModule
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